diff options
| author | Lawrence Chang <lawrence.chang@intel.com> | 2024-10-25 15:52:57 +0800 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2024-11-06 16:47:25 +0000 |
| commit | d88eeae6161af3d131abb90d7164c59fa620670d (patch) | |
| tree | 02c1f222f4e8fb8e416636e3f10aba94bdd1593a /src/soc/intel | |
| parent | 6a8e8459a89adcbdbb12b6ebb430a7ddafe20752 (diff) | |
soc/intel/jasperlake: add support for RP LTR mechanism
Reserve Root Port LTR mechanism in FSP, in case some devices
need to optimize LTR.
BUG=366383364
TEST=Tested on Awasuki with RTL8852BE
use lspci -xxx to get PCIE config space dump, and LTR Mechanism Enable
bit is offset 68h[10].
00:1c.0 PCI bridge: Intel Corporation Device 4dbf (rev 01)
00: 86 80 bf 4d 07 05 10 00 01 00 04 06 10 00 81 00
10: 00 00 00 00 00 00 00 00 00 01 01 00 20 20 00 20
20: c0 7f c0 7f f1 ff 01 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 0b 04 12 00
40: 10 80 42 01 00 80 00 00 00 00 10 00 13 4c 72 08
50: 43 00 11 70 00 b2 3c 00 00 00 40 01 08 00 00 00
60: 00 00 00 00 37 08 00 00 00 04 00 00 0e 00 00 00
70: 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 05 90 01 00 38 02 e0 fe 00 00 00 00 00 00 00 00
90: 0d a0 00 00 86 80 bf 4d 00 00 00 00 00 00 00 00
a0: 01 00 03 c8 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 01 10 00 07 42 18 01 40 08 00 9e 09 00 00 00 00
e0: 00 03 e3 00 00 00 00 00 16 00 10 00 00 00 00 00
f0: 50 01 00 00 00 00 00 4c b5 0f 02 01 04 00 00 84
Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f
Signed-off-by: Lawrence Chang <lawrence.chang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84866
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: David Ruth <druth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/jasperlake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/fsp_params.c | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 53bf34f0bf..00fac3c10f 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -152,6 +152,9 @@ struct soc_intel_jasperlake_config { /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ bool PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + /* PCIe LTR: Enable (1) / Disable (0) */ + uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 85664ce18b..3bad533424 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -190,6 +190,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + /* PCIe Root Ports LTR mechanism */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) + params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; + /* Configure FIVR RFI related settings */ params->FivrRfiFrequency = config->FivrRfiFrequency; params->FivrSpreadSpectrum = config->FivrSpreadSpectrum; |