diff options
| -rw-r--r-- | src/soc/intel/jasperlake/chip.h | 3 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/fsp_params.c | 4 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 53bf34f0bf..00fac3c10f 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -152,6 +152,9 @@ struct soc_intel_jasperlake_config { /* Probe CLKREQ# signal before enabling CLKREQ# based power management.*/ bool PcieRpClkReqDetect[CONFIG_MAX_ROOT_PORTS]; + /* PCIe LTR: Enable (1) / Disable (0) */ + uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 85664ce18b..3bad533424 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -190,6 +190,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + /* PCIe Root Ports LTR mechanism */ + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) + params->PcieRpLtrEnable[i] = config->PcieRpLtrEnable[i]; + /* Configure FIVR RFI related settings */ params->FivrRfiFrequency = config->FivrRfiFrequency; params->FivrSpreadSpectrum = config->FivrSpreadSpectrum; |