diff options
| author | Naresh Solanki <naresh.solanki@9elements.com> | 2024-10-11 22:51:38 +0530 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2024-10-16 15:27:03 +0000 |
| commit | 1d18513ad5d10034effb0b10e7db11487fa7e6cf (patch) | |
| tree | 8fc2505c8d8146784a3a78312132ea4b93dcb6fa /src/soc/intel | |
| parent | d11ee4952194934ebdea4ef5481b9095958eb247 (diff) | |
soc/intel/xeon_sp: Allow Memory POR independent of RMT
TEST=Build & boot in IBM SBP1 system. Verified the settings are effective in FSP logs.
Change-Id: I4341ead89a2683f64c834a6981ba316fcfef4f9a
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84741
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/Kconfig | 3 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/spr/romstage.c | 4 |
2 files changed, 3 insertions, 4 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index b84a8ff267..6fad812941 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -174,10 +174,9 @@ config ENABLE_RMT Enable Rank Margining Tool. This option is intended for debugging and validation and should normally be disabled. -config RMT_MEM_POR_FREQ +config MEM_POR_FREQ bool "Enforce Plan Of Record restrictions for DDR5 frequency and voltage" default n - depends on ENABLE_RMT help When RMT is enabled. Select this option to enforce Intel Plan Of Record(POR) restriction on DDR5 frequency & voltage settings. diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index b05c7e76fd..4d95a33365 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -241,9 +241,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) mupd->FspmConfig.serialDebugMsgLvl = 0x3; mupd->FspmConfig.AllowedSocketsInParallel = 0x1; mupd->FspmConfig.EnforcePopulationPor = 0x1; - if (CONFIG(RMT_MEM_POR_FREQ)) - mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; } + if (CONFIG(MEM_POR_FREQ)) + mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; /* SPR-FSP has no UPD to disable HDA, so do it manually here... */ if (!is_devfn_enabled(PCH_DEVFN_HDA)) |