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authorSean Rhodes <sean@starlabs.systems>2024-07-18 20:35:29 +0100
committerSean Rhodes <sean@starlabs.systems>2024-10-11 08:31:58 +0000
commitbc0db40ed553afb24bef6ddc1754ee2408c247c2 (patch)
tree123778c9062ea8e583487046df2f85f0701d73d4 /src/soc/intel
parent1d535eb467c3a9119ec3022494ded8b06bf7ab28 (diff)
soc/intel/cnvi: Add PRR method for CNVi Reset
Add a _PRR method that the OS can use to reset the wireless. This is only used for integrated solutions and depends on the CNMT Mutex that's created with `drivers/usb/acpi`. Whilst new ACPI is added, the behavior of existing boards won't be changed unless they configure the accompanying Bluetooth device. Intel document #559910 details this. Change-Id: I25e8462780badcad88b13052a6eb282c83af5def Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83557 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/common/block/cnvi/cnvi.c189
1 files changed, 189 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/cnvi/cnvi.c b/src/soc/intel/common/block/cnvi/cnvi.c
index afe08c5120..9759b542af 100644
--- a/src/soc/intel/common/block/cnvi/cnvi.c
+++ b/src/soc/intel/common/block/cnvi/cnvi.c
@@ -98,6 +98,195 @@ static void cnvw_fill_ssdt(const struct device *dev)
}
acpigen_pop_len();
+
+/*
+ * Name (RSTT, Zero)
+ */
+ acpigen_write_name_integer("RSTT", 0);
+
+/*
+ * PowerResource(WRST, 5, 0)
+ * {
+ * Method(_STA)
+ * {
+ * Return (0x01)
+ * }
+ * Method(_ON, 0)
+ * {
+ * }
+ * Method(_OFF, 0)
+ * {
+ * }
+ * Method(_RST, 0, NotSerialized)
+ * {
+ * Local0 = Acquire (\_SB.PCI0.CNMT, 1000)
+ * If ((Local0 == Zero))
+ * {
+ * CFLR ()
+ * PRRS = One
+ * If ((RSTT == One))
+ * {
+ * If (((PCRR (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR) & CNVI_ABORT_REQUEST) == Zero))
+ * {
+ * Local2 = Zero
+ * If ((GBTE() == One))
+ * {
+ * BTRK (Zero)
+ * Sleep (105)
+ * Local2 = One
+ * }
+ * PCRO (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR, CNVI_ABORT_REQUEST | CNVI_ABORT_ENABLE)
+ * Sleep (10)
+ * Local1 = PCRR (CNVI_SIDEBAND_ID, CNVI_ABORT_PLDR)
+ * If ((((Local1 & CNVI_ABORT_REQUEST) == Zero) && (Local1 & CNVI_READY)))
+ * {
+ * PRRS = CNVI_PLDR_COMPLETE
+ * If ((Local2 == One))
+ * {
+ * BTRK (One)
+ * Sleep (105)
+ * }
+ * }
+ * Else
+ * {
+ * PRRS = CNVI_PLDR_NOT_COMPLETE
+ * }
+ * }
+ * Else
+ * {
+ * PRRS = CNVI_PLDR_TIMEOUT
+ * }
+ * }
+ * Release (\_SB.PCI0.CNMT)
+ * }
+ * }
+ * }
+ *
+ * Name (_PRR, Package (0x01)
+ * {
+ * WRST
+ * })
+ */
+ acpigen_write_power_res("WRST", 5, 0, NULL, 0);
+ {
+ acpigen_write_method("_STA", 0);
+ {
+ acpigen_write_return_integer(1);
+ }
+ acpigen_pop_len();
+
+ acpigen_write_method("_ON", 0);
+ acpigen_pop_len();
+
+ acpigen_write_method("_OFF", 0);
+ acpigen_pop_len();
+
+ acpigen_write_method("_RST", 0);
+ {
+ acpigen_write_store();
+ acpigen_write_acquire("\\_SB.PCI0.CNMT", 1000);
+ acpigen_emit_byte(LOCAL0_OP);
+
+ acpigen_write_if_lequal_op_int(LOCAL0_OP, 0);
+ {
+ acpigen_emit_namestring("CFLR");
+
+ acpigen_write_store_int_to_namestr(1, "PRRS");
+
+ acpigen_write_if_lequal_namestr_int("RSTT", 1);
+ {
+ acpigen_write_store();
+ acpigen_emit_namestring("\\_SB.PCI0.PCRR");
+ acpigen_write_integer(CNVI_SIDEBAND_ID);
+ acpigen_write_integer(CNVI_ABORT_PLDR);
+ acpigen_emit_byte(LOCAL0_OP);
+
+ acpigen_emit_byte(AND_OP);
+ acpigen_emit_byte(LOCAL0_OP);
+ acpigen_write_integer(CNVI_ABORT_REQUEST);
+ acpigen_emit_byte(LOCAL0_OP);
+
+ acpigen_write_if_lequal_op_int(LOCAL0_OP, 0);
+ {
+ acpigen_write_store_int_to_op(0, LOCAL2_OP);
+ acpigen_write_if_lequal_namestr_int("\\_SB.PCI0.GBTE", 1);
+ {
+ acpigen_emit_namestring("BTRK");
+ acpigen_emit_byte(0);
+
+ acpigen_write_sleep(105);
+
+ acpigen_write_store_ops(1, LOCAL2_OP);
+ }
+ acpigen_pop_len();
+
+ acpigen_emit_namestring("\\_SB.PCI0.PCRO");
+ acpigen_write_integer(CNVI_SIDEBAND_ID);
+ acpigen_write_integer(CNVI_ABORT_PLDR);
+ acpigen_write_integer(CNVI_ABORT_REQUEST | CNVI_ABORT_ENABLE);
+
+ acpigen_write_sleep(10);
+
+ acpigen_write_store();
+ acpigen_emit_namestring("\\_SB.PCI0.PCRR");
+ acpigen_write_integer(CNVI_SIDEBAND_ID);
+ acpigen_write_integer(CNVI_ABORT_PLDR);
+ acpigen_emit_byte(LOCAL0_OP);
+
+ acpigen_emit_byte(AND_OP);
+ acpigen_emit_byte(LOCAL0_OP);
+ acpigen_write_integer(CNVI_ABORT_REQUEST);
+ acpigen_emit_byte(LOCAL1_OP);
+
+ acpigen_emit_byte(AND_OP);
+ acpigen_emit_byte(LOCAL0_OP);
+ acpigen_write_integer(CNVI_READY);
+ acpigen_emit_byte(LOCAL3_OP);
+
+ acpigen_write_if_lequal_op_int(LOCAL1_OP, 0);
+ {
+ acpigen_write_if_lequal_op_int(LOCAL3_OP, 1);
+ {
+ acpigen_write_store_int_to_namestr(CNVI_PLDR_COMPLETE, "PRRS");
+
+ acpigen_write_if_lequal_op_int(LOCAL2_OP, 1);
+ {
+ acpigen_emit_namestring("BTRK");
+ acpigen_emit_byte(1);
+ acpigen_write_sleep(105);
+ }
+ acpigen_pop_len();
+ }
+ acpigen_pop_len();
+ }
+ acpigen_write_else();
+ {
+ acpigen_write_store_int_to_namestr(CNVI_PLDR_NOT_COMPLETE, "PRRS");
+ }
+ acpigen_pop_len();
+ }
+ acpigen_write_else();
+ {
+ acpigen_write_store_int_to_namestr(CNVI_PLDR_TIMEOUT, "PRRS");
+ }
+ acpigen_pop_len();
+ }
+ acpigen_pop_len();
+ acpigen_write_release("\\_SB.PCI0.CNMT");
+ }
+ acpigen_pop_len();
+ }
+ acpigen_pop_len();
+ }
+ acpigen_write_power_res_end();
+
+ acpigen_write_name("_PRR");
+ {
+ acpigen_write_package(1);
+ acpigen_emit_namestring("WRST");
+ }
+ acpigen_pop_len();
+
acpigen_write_scope_end();
}