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Change-Id: I0c965e598e260ff8129aa07fb9fc5bf6e784e1d8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This reverts commit d5018a8f78b9e1f0b7d3d1be298cba9716b10c6c.
Reason for revert: Breaks boot on Whiskey Lake-U boards
Both System76 and Purism have had memory initialization failures
when this patch is applied, with the following error message:
Failed to accommodate FSP reserved memory request!
An extra 4096 bytes needs to be reserved for the FSP on these
systems, and reinstating the PTT reservation does this as
expected. PTT is enabled for the System76 galp3-c in the
ME configuration, which is why the behaviour is different.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
CC: Matt DeVillier <matt.devillier@gmail.com>
CC: Subrata Banik <subrata.banik@intel.com>
Change-Id: Ib82f02c4a2b1cd2dbf95d4ca4a9edd314e78edd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The current DCACHE_BSP_STACK_SIZE is set to 128KiB for CML & ICL when
FSP uses the same stack provided by coreboot. This patch updates it to
129KiB since the default value of DCACHE_BSP_STACK_SIZE must be
the sum of FSP-M stack requirement (128KiB) and CB romstage
stack requirement (~1KiB).
BUG=b:140268415
TEST=Build and boot CML-Hatch.
Change-Id: Icedff8b42e86dc095fb68deb0b8f80b2667cfeda
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36032
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2a94c3b6282e9915fd2b8136b124740c8a7b774c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This corrects the LPC/eSPI lock bit from bit 2 to bit 1 in accordance
with doc#332691-003EN and doc#334819-001.
Change-Id: I45335909b1f2b646e4fafedd78cb1aaf7052d60c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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It turned on some SKUs FSP hangs in Notify stage if IIO root ports are
disabled after MemoryInit. To address that hide IIO root ports earlier
in romstage.
TEST=the patch was ran on affected HW and success was reported
Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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As VGA_ROM_RUN and libgfxinit are mutually exclusive in Kconfig,
we don't have to guard all the VGA BIOS if's and can assume
gfx_get_init_done() returns 0 until all the quirks are handled.
Then, we can run libgfxinit.
Change-Id: Id5d0c2c12b1ff8f95ba4e0223a3e9aff27547acd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/20100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Port the backlight-PWM handling from Skylake instead of the previously
used Haswell version. We use a 200Hz PWM signal for all boards. Which
is higher than the previous devicetree value, 183Hz, but that was over-
ridden by the VBIOS anyway. 200Hz is still very low, considering LED
backlights, but accurate values are unknown at this time.
Lynx Point, the PCH for Haswell and Broadwell, is a transition point
for the backlight-PWM config. On platforms with a PCH, we have:
o Before Lynx Point:
The CPU has no PWM pin and sends the PWM duty-cycle setting
to the PCH. The PCH can choose to ignore that and use its own
setting (BLM_PCH_OVERRIDE_ENABLE).
We use the CPU setting on these platforms.
o Lynx Point + Haswell:
The CPU has an additional PWM pin but can be set up to send
its setting to the PCH as before. The PCH can still choose
to ignore that.
We use the CPU setting with Haswell.
o Lynx Point + Broadwell:
The CPU can't send its setting to the PCH anymore. BLM_PCH_
OVERRIDE_ENABLE must always be set(!) if the PCH PWM pin is
used (it virtually always is).
We have to use the PCH setting in this case.
o After Lynx Point:
Same as with Broadwell, only BLM_PCH_OVERRIDE_ENABLE is
implied and the bit not implemented anymore.
Change-Id: I1d61d9b3f1802ebe18799fc4d06f1f1d3b54c924
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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APL unhides the P2SB device in coreboot already. Do the same on SKL/KBL.
As the coreboot PCI allocator needs to be able to find the device,
unhide it after FSP-S.
The device is hidden in the SoC finalize function already and not visible
in the OS, as more P2SB device IDs have been added.
Other SoCs aren't updated, because they are too broken.
Fixes "BUG: XXX requests hidden ...." warnings in coreboot log.
Tested on Supermicro X11SSH-TF.
Change-Id: I0d14646098c34d3bf5cd49c35dcfcdce2c57431d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner
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On Hyper-Threading enabled platforms the MSR_PRMRR_PHYS_MASK was written
when already locked by the sibling thread. In addition it loads microcode
updates on all threads.
To prevent such race conditions only call the code on one thread, such
that the MSRs are only written once per core and the microcode is only
loaded once for each core.
Also add comments that describe the scope of the MSR that is being
written to and mention the Intel documents used for reference.
Fixes crash in SGX MP init.
Tested on Supermicro X11SSH-TF.
Change-Id: I7102da028a449c60ca700b3f9ccda9017aa6d6b5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35312
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rework SGX enable status in a clean way without using a global variable.
Change-Id: Ida6458eb46708df8fd238122aed41b57ca48c15b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Devices behind LPC can expose more buses (e.g. I2C on a super-i/o).
So we should scan buses on LPC devices, too.
Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29474
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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scan_usb_bus() and root_dev_scan_bus() had the very same implementation.
So rename the latter to scan_static_bus() and use that for both cases.
Change-Id: If0aba9c690b23e3716f2d47ff7a8c3e8f6d82679
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31901
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The new name should reflect better what this function does, as that
is only one specific step of the scanning.
Change-Id: I9c9dc437b6117112bb28550855a2c38044dfbfa5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31900
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.
Change-Id: I1a8675a4e613a8efc135b05cde36f166acaa7ed4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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The code is compiled on SKL/KBL, but the P2SB PCI IDs were missing.
Add them to make sure that the BAR0 doesn't change when running PCI
resource allocation.
Change-Id: I7cffbbc7d15dad14cccd122a081099b51dc1ce07
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I02c08b847fa1523e3296bdf9e3db5a7a322df72e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.
Change-Id: Id78e594ae6490d39df76317f8fc3381fe681dd6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Some VR parameter values for KBL-U with GT3 graphics are different from
values for other CPUs in this series [1]. However, GT3 iGPU will never
be detected, since the igd_id variable is compared with the LPC device
PCI ID. The patch fixes this bug.
[1] page 109, 7th Generation Intel(R) Processor Families for U/Y
Platforms and 8th Generation Intel(R) Processor Family for U Quad
Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019.
Document Number: 334661-006
Change-Id: I33527d90550a1de78c9375d3d3b0e046787a559b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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According to the documentation[1], the Loadline in the unslased GT VR
domain should be 2 mOhms for KBL-U (2 Core, GT3 + OPC).
[1] page 109, 7th Generation Intel(R) Processor Families for U/Y
Platforms and 8th Generation Intel(R) Processor Family for U Quad
Core and Y Dual Core Platforms. Datasheet, Volume 1. January 2019.
Document Number: 334661-006
Change-Id: I433036e76d456a725ab27cf57c9bc2fe01a7ace1
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35781
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Adds missing Intel HD/Iris iGPU PCI IDs for Kaby Lake processors and
updates the platform report for these devices.
These changes are in accordance with the documentation:
[*] page 10, Intel(R) Open Source HD Graphics and Intel Iris(TM) Plus
Graphics for the 2016 - 2017 Intel Core(TM) Processors, Celeron(TM)
Processors, and Pentium(TM) Processors based on the "Kaby Lake"
Platform. Programmer's Reference Manual. Volume 4: Configurations.
January 2017, Revision 1.0
Doc Ref # IHD-OS-KBL-Vol 4-1.17
[*] Linux kernel sources: include/drm/i915_pciids.h
Change-Id: I1cd1e4ab82f756141f8f13edf1c17f726166dffb
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Adds missing Intel HD/Iris iGPU PCI IDs for Skylake processors
These changes are in accordance with the documentation:
[*] page 11-12, Intel(R) Open Source HD Graphics, Intel Iris(TM)
Graphics, and Intel Iris(TM) Pro Graphics, Programmer's Reference
Manual. Volume 4: Configurations. May 2016, Revision 1.0
Doc Ref # IHD-OS-SKL-Vol 4-05.16
Change-Id: I0ba6e58ec3916dceea00519ac5a51503573e8935
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35493
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the DC Current Specifications [1], the current limit for
the graphical VR domain (Iccmax_gt) isn't same for different Kaby Lake S
CPUs. This value should depend on the iGPU model and processor TDP:
+---------------------+-----+------------+
| Segment | TDP | Icc_max GT |
+---------------------+-----+------------+
| Dual Core GT2/GT1 | 35W | |
| Dual Core GT2 | 51W | 48 A |
| Dual Core GT1 | 54W | |
+---------------------+-----+------------+
| Quad Core GT2 | 35W | 35 A |
+---------------------+-----+------------+
| Quad Core GT2 | 65W | 45 A |
| Quad Core GT2 K-SKU | 91W | |
+---------------------+-----+------------+
This patch adds the remaining Iccmax_gt current limit values from the
documentation [1].
[1] 7th Generation Intel(R) Processor Families for S Platforms and
Intel(R) Core(TM) X-Series Processor Family Datasheet, Volume 1,
December 2018, Document Number: 335195-003
Change-Id: I19766e4f8fab6b48565b65ed4cf13efbc213e654
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Add defines to have some more readable code for devcietree.cb.
BUG=N/A
TEST=4K HDMI monitor and LCD working fine on Facebook FBG-1701
Change-Id: Ifc1a7657a528d1fc570dd16df66b078e37e014cb
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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These were unused and somewhat cryptic, assumed purpose was to store
pre-CBMEM timestamps in various PCI config space locations.
Change-Id: I074294446501d49a9bd3c823a2a794c33f443168
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35731
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel adopted xx_DEVFN_xx naming for macros expanding to
PCI_DEVFN() starting with apollolake. The ones named
xx_DEV_FUNC are being renamed, or dropped, if they
were generally not used at all for a platform.
Change-Id: Ice1062d10b793dcbeb5b2ce9e2788fd3b6b6250b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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When creating the IRQ routing, referenced device and
function number are always of the same PCI device.
Change-Id: Ifc4795245187f8d70650242a56e6ce771ef2167a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35735
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I953e9a7746232b4c40deca55eb6cb3bd7af91496
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The function does not otherwise need dev.
Change-Id: I75d3283b537151258ed48f7e4e0991dff53a803c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35670
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The previously provided device path made no difference, all
integrated PCI devices point back to the same chip_info
structure.
Change reduces the exposure of various SA_DEVFN_xx and
PCH_DEVFN_xx from (ugly) soc/pci_devs.h.
Change-Id: Ibf13645fdd3ef7fd3d5c8217bb24d7ede045c790
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Make the the FSP Parameter PchHdaVcType a devicetree setting and make
use of it in the devicetrees of all boards that currently set it.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ibafc3b6bd2495658f2bd634218042ec413a89f5e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
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This is a PCI standard register, no need to alias its
definitions under different names.
Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Apparently romcc-bootblock just barely built without
XMM registers.
Change-Id: Ie7b1101f47c2dfb718bef99f8c05f9d575c821cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The new macro name contains the number of cores:
PCI_DEVICE_ID_INTEL_SKL_ID_H_4 - 4 core
PCI_DEVICE_ID_INTEL_SKL_ID_H_2 - 2 core
Change-Id: I190181b213d55865aa577ae5baff179fef95afde
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35302
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make sure to match devices on the root bus only. This fixes an issue
where the SoC returned "MCHC" as ACPI name for devices behind bridge
devices, as the DEVFN matched.
Fixes observed "ACPI exception: AE_NOT_FOUND" in dmesg, as the ACPI
path no longer contains invalid names.
Tested on Supermicro X11SSH-TF.
Change-Id: I6eca37a1792287502a46a90144f2f0d8e12ae5d4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change in ssus_disable_internal_pull() is for romcc
compatibility.
Change-Id: Ib72a669a3b5cd90e74d917f74f35453a85941658
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35600
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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If VBOOT is used on a mainboard based on fsp_broadwell_de then VBOOT
needs to be able to write to its NV data which may be stored on the SPI
flash. Enable write access to the SPI flash on SoC level. If the
mainboard does not use VBOOT the linker will drop the extra code. The
benefit is that this code is at least compiled and therefore build
tested with fsp_broadwell_de.
Change-Id: I90a2d30f5749c75df2b286dce6779f10dde62632
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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It is safe to assume this to be copy-paste from eg. i945
where registers of said PCI device were read.
Change-Id: I387b7fd6caf317543a6438f973d9e1d96e418de3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35668
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The filename chip.h has a special purpose with the generation
of static devicetree, where the configuration structure name matches
the path to the chip.h file. For example, soc/intel/skylake/chip.h
defines struct soc_intel_skylake_config.
The renamed file did not follow this convention and the structure it
defines would conflict with one defined soc/intel/common/chip.h if such
is ever added.
Change-Id: Id3d56bf092c6111d2293136865b053b095e92d6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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TEST=just build it
Change-Id: I34aee507b8c322c816f92cfcae177c069c749ed7
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Removed mkhi_hdr structure definition from multiple SOCs, and moved to common.
TEST=Built code for Hatch, apollolake boards.
Change-Id: Ifeba0ed4d98975049179d1b47fb22c06a927dc29
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35545
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add function to hide IIO PCIe root ports.
TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3]
and make sure OS does not detect built-in NIC.
Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Change-Id: I5bd95b3580adc0f4cffa667f8979b7cf08925720
Signed-off-by: Michael Niewöhner <michael.niewoehner@8com.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Change-Id: I189eb8ffce2f0735ad9ba603b1d96786aa00fafb
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Currently "DIMM numbers" increase monotonically for all the channels. However,
commonly DIMMS are numerated on per-channel basis. This change makes numeration
match the convention.
TEST=on OCP monolake, run dmidecode tool and see that "Locator" field matches
expectation.
Change-Id: I3e7858545471867a0210e1b9ef646529b8e2a31c
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35318
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Intel's EDS says "1 = GPIO Driver Mode. GPIO input event updates are
limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates
are masked." Therefore, the GPI_GPIO_DRIVER_SCI option for pad
configuration is meaningless, as any GPE will be masked if the GPIO
driver is set as owner.
Change-Id: Ia0cd0041dfc985cbe388cb89a4026038c7fb4383
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35460
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Below new functions are added:
* send_hmrfpo_enable_msg() - Sends HMRFPO Enable command to CSE. This
API sets ME in SEC_OVERRIDE mode. The mode prevents CSE to execute SPI I/O
cycles to CSE region, and unlocks the CSE region to perfom updates to it.
* send_hmrfpo_get_status_msg() - Sends HMRFPO Get Status command to CSE
TEST=Verified sending HMRFPO_ENABLE & HMRFPO_GET_STATUS HECI commands on
CML RVP & hatch board
Change-Id: I559bc4641e12df7ed39b1c97097bf068f9a232db
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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send_heci_reset_req_message() is defined in multiple places,
hence move it to common code.
TEST=Verified on CMLRVP/Hatch/Soraka/Bobba/Dragon Egg boards.
Change-Id: I691fc0610356ef1f64ffa7cc4fe7a39b1344cc16
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35228
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds SATA parameters for SpinUp, HotPlug and TestMode to the
Skylake FSP 2.0 interface.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I7ba67879b78c2cb0fd0b0ce832140b213edd5884
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35186
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I80c92f744fb9a6c3788b8b9ba779deef76e58943
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33530
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Guards are required due to different PCI accessor
signatures.
Change-Id: I60e87f16a48565917f6ee9d05cc59d2b9373270c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35381
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I35b44967de4e8d9907dc887fe35407bcaf334adc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35379
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I898188d31fcfd153eb95d0a7324fa9fd85316e3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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FSP BIOS 212 / 07.00.6C.40 for CNL/WHL supports FSP to use coreboot stack.
This change selects common stack config, that enables coreboot to support
share stack with FSP.
TEST=Boot to OS on WHL platform
Change-Id: I0778ee21cb4f66b8ec884b77788c05a73c609be6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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PchPwrOptEnable FSP UPD is for internal testing and not really available
in externally released FSP source hence assigning this UPD using devicetree
config dmipwroptimize doesn't do anything.
TEST=Build and boot sarien/arcada.
Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Change-Id: I01e1e356936b85b186d9bd5f1c1e5e3a1157a30b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33732
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Host FW status 1 (FWSTS1/HFSTS1) register definition is common across SoCs,
hence move it to common. Also add below helper function,
* wait_cse_sec_override_mode() - Polls ME status for "HECI_OP_MODE_SEC_OVERRIDE".
It's a special CSE mode, the mode ensures CSE does not trigger any
spi cycles to CSE region.
* set_host_ready() - Clears reset state from host CSR.
TEST=Verified CSE recover mode on CML RVP & Hatch board
Change-Id: Id5c12b7abdb27c38af74ea6ee568b42ec74bcb3c
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
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CML FSP now provides a provision to configure the SATA devslp
GPIO pad reset configuration. This config would help set the
the required pad reset configuration.
BUG=b:133000685
Change-Id: I4eaea9c6da67f1274ad3e392046a68cddc1b99b6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This patch helps to save additional ~19ms of booting time in
normal boot and s3 resume on CML-hatch.
BUG=b:140008206
TEST=Verified normal boot time on CML-Hatch with latest coreboot
Without this CL:
Total Time: 929ms
With this CL: (TSEG marked as WB)
Total Time: 910ms
For test marked TSEG as WP/WC:
Total Time: ~920ms
Change-Id: Ie92d2c9e50fa299db1cd8c57a6047ea3adaf1452
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35026
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes dedicated function call to make TSEG region cache
from soc and refers to postcar_enable_tseg_cache().
BUG=b:140008206
Change-Id: I18a032b43a2093c8ae86735c119d8dfee40570b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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For CML & ICL, FSP requires at least heap = 0x10000 and stack = 0x20000.
Refer to FSP integration guide to know the exact FSP requirement.
BUG=b:140268415
TEST=Build and boot CML-Hatch and ICL.
Change-Id: Ic1463181b4a9dca136d00cb2f7e3cce4f7e57bd6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35301
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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me_read_config32() is defined in multiple places, move it to common
location. Also, this function is usually used for reading HFSTS
registers, hence move the HFSTS register definitions to common location.
Also add a funtion to check if the CSE device has been enabled in the
devicetree and it is visible on the bus. This API can be used by
the caller to check before initiating any HECI communication.
TEST=Verified reading HFSTS registers on CML RVP & Hatch board
Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35225
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Restrict the use of symbol names _car_global_[start|end]
to be used exclusively with CAR_GLOBAL_MIGRATION=y.
They just alias the start and end of .bss section in CAR.
Change-Id: I36c858a4f181516d4c61f9fd1d5005c7d2c06057
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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These have become aliases to _car_global_[start|end].
Change-Id: Ibdcaaafdc0e4c6df4a795474903768230d41680d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Tested on Supermicro X11SSH-TF.
Change-Id: I3ebab68ff868c78105bb4b35abffb92f3ccf1705
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Modify intel/fsp_broadwell_de such that timestamp_init() is
before raminit (and CAR teardown of FSP1.0), adding two new
early timestamps while doing so.
Other FSP1.0 platforms fsp_baytrail and fsp_rangeley already
do it this way.
Change-Id: I3b73e4a61622f789a49973a43b21e8028bcb8ca8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35279
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In the very early days of FSP 1.0 this did not work so
we kept it disabled.
Change-Id: I8a88be6df335598d4c6007a8b7ff307b293e1f97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Aggregate sending and receiving HECI messages into a single function.
TEST=Verified sending and receiving reply HECI message on CML RVP & Hatch board
Change-Id: Ic95239eef8591d3aadf56a857c97f3f1e12b16ac
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35224
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch disables FSP-S SPI lockdown UPDs and lets coreboot perform
SPI lockdown (i.e.flash register DLOCK, FLOCKDN, and WRSDIS before
end of post) in ramstage.
BUG=b:138200201
TEST=FSP debug build suggests those UPDs are disable now.
Change-Id: Id7a6b9859e058b9f1ec1bd45d2c388c02b8ac18c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
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Decide if HECI1 should be hidden prior to boot to OS.
BUG=none
TEST=Boot to OS, verify if Heci1 is disabled on hatch system
using FSP 1344.
Change-Id: I7c63316c8b04fb101d34064daac5ba4fdc05a63c
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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This patch adds Lewisburg C62x Series PCH support by adding the
Production and Super SKUs of the following PCI devices:
- LPC or eSPI Controllers,
- PCI Express Root Ports,
- SSATA and SATA Controllers,
- SMBus,
- SPI Controller,
- ME/HECI,
- Audio,
- P2SB,
- Power Management Controller.
These changes are in accordance with the documentation:
[*] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
(PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I7eaf2c1bb725ffed66f86c023c415ad17fe5793d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
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Add printing SPD data for debug usage.
BUG=b:139397313
BRANCH=N/A
TEST=Tested the on Hatch and checked cbmem log.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1e257a8ea6ff9c906267841819d2a4b62a9e0b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The P2SB PCI device can be "hidden", which causes all sorts of
nightmares and bugs. Moreover, FSP tends to hide it, so finding
a good solution to this problem is impossible with FSP into the mix.
Since the values for IBDF and HBDF were already hardcoded as FSP
parameters, define them as macros and use these values directly to
generate the DRHD.
Change-Id: I7eb20182380b953a1842083e7a3c67919d6971b9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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BUG=b:139798422, b:129839774
TEST=Able to build and boot KBL/CML/ICL.
Change-Id: I341eec13d275504545511904db0acd23ad34e940
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35234
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add fan based active cooling for TSR sensors temperature range.
BUG=b:138966929
BRANCH=None
TEST=Verified Fan control functionality for TSR sensors on Hatch.
Change-Id: I957ae96cf6fa7d2467e73155d64f76a6bd652e31
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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tsc_freq_mhz() had a static table of Intel CPU families and crystal
clock, but it is possible to calculate the crystal clock speed dynamically,
and this is preferred over hardcoded table.
On SKL/KBL/CML CPUID.15h.ecx = nominal core crystal clock = 0 Hz
hence we had to use static table to calculate crystal clock.
Recommendation is to make use of CPUID.16h where crystal clock frequency
was not reported by CPUID.15h to calculate the crystal clock.
BUG=b:139798422, b:129839774
TEST=Able to build and boot KBL/CML/ICL.
Change-Id: If660a4b8d12e54b39252bce62bcc0ffcc967f5da
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35148
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ide10223e7fc37a6c4bfa408234ef3efe1846236a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I09292c2776309982cfb4d72012991bf7725b75fb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32912
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enables Gaussian Mixture Model (GMM) only if the corresponding pci
device is enabled in the device tree
Tested on Asrock H110M DVS motherboard
Change-Id: I21409adf85b70bccc30dd8e12a03ad7921544b3c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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* Add Kconfig to enable TXT
* Add possibility to add BIOS and SINIT ACMs
* Set default BIOS ACM alignment
* Increase FIT space if TXT is enabled
The following commits depend on the basic Kconfig infrastructure.
Intel TXT isn't supported until all following commits are merged.
Change-Id: I5f0f956d2b7ba43d4e7e0062803c6d8ba569a052
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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According to the documentation, Sunrise PCH-H [1,2] and Lewisburg PCH
[3] supports up to 16 PCIe ports. However, ACPI contains a description
for only 12 ports. This patch adds ACPI code for missing ports
[1] page 182, Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2,
December 2018, Document Number: 332690-005EN
[2] page 180, Intel (R) 200 Series and Intel (R) Z370 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 1 of 2,
October 2017, Document Number: 335192-003
[3] page 39, Intel(R) C620 Series Chipset Platform Controller Hub
(PCH) Datasheet, May 2019. Document Number: 336067-007US
Change-Id: I954870136e0c8e5ff5d7ff623c7a6432b829abaf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Removes PCI_DEVICE_ID_INTEL_SKL_ID_DT because this PCI Id duplicates
PCI_DEVICE_ID_INTEL_SKL_ID_S_4 (0x191f)
Change-Id: I028a22d6a42c040f5991a03def3e410f515c1c7f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ifb2adcdef7265d43cb2bf6886f126f1a17bf08a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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SoC was unintentionally flagged with SMM_TSEG when default
values were assigned.
Change-Id: I83202316f41ead66c7f69cad68dafaeccd09df66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I9297d5b4f7c8ed703fb8772739531cdd7d5ca5f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There will be inlined smm_lock() that would conflict
with this special case.
Change-Id: I6752cbcf4775f9c013f0b16033b40beb2c503f81
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34874
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on OCP/Wedge100s:
No error is visible in console output, still boots to OS.
Change-Id: I986bbe978d3f68693b2d4538ccbcc11cdbd23c6a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34745
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Implement sa_get_tseg_base and sa_get_tseg_size.
Used by Intel TXT and the new SMM API.
Tested on OCP/Wedge100S.
Change-Id: I22123cbf8d65b25a77fbf72ae8411b23b10c13b4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I95f1685f9b74f68fd6cb681a614e52b8e0748216
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34738
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The MSRs were already named as PRMRR in broadwell, just
mismatching with the rest of the code. All later devices
use the names PRMRR and UNCORE_PRMRR for these MSRs.
Reflect the name change in structures and local variables.
Change-Id: Id825ba2c083d0def641dd9bf02d3b671d85b1e35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34825
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4af661f68c158cbed591fe017d4bc25239bddd37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34758
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4e9de9c7f5decd784d881e5a733e995522be5226
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34757
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I99440539d7b7586df66395776dcd0b4f72f66818
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34964
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I84b1fad52d623a879f00c3f721f480f58d7d6d8a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34894
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:139798422
TEST=Build and boot CMLRVP.
Change-Id: Ib79995606f6da12bfa7aa5c1a1dbc0b972bb1688
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
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Currently, we don't have UPDs to set emmc settings per mainboard on CML.
This code change is to create mmc.c to provide interface to override dll
settings per mainboard.
Notice: set_mmc_dll function will override the dll values in FSP.
BUG=b:131401116
BRANCH=none
TEST=Boot to OS and confirm the dll values have been overridden.
Change-Id: Ib3c72b9851f41585ec099d8ae83a721af87ed383
Signed-off-by: Kane Chen <kane.chen@intel.com>
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ic2677bcf9f2f79c4db725ebcf342a8575ee7bc38
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34739
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Done just for future review convenience.
Change-Id: I9cfb0a8177c8ca18947ef0109550a36aa4333383
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34910
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Tested on Mono Lake
TEST=Note the kernel log:
hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
hpet0: 8 comparators, 64-bit 14.318180 MHz counter
Change-Id: Idae9a7d3d4233037214d6203996bf44fe5f3a845
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35027
Reviewed-by: Johnny Lin
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch includes common romstage code to setup the console
and load postcar.
Fix booting regression issue on all latest IA-SOC introduced by CB:34893
Change-Id: I9da592960f20ed9742ff696198dbc028ef519ddf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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