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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-16 17:37:48 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-08-28 22:49:27 +0000
commit3e7727908c3137442742a96079def34bb966faaf (patch)
treedb04b88af27e0c76e4ea43892794710fb4fd2148 /src/soc/intel
parent81100bf7ff62c4ee53214afb82f2fa9112d109b6 (diff)
google/rambi,intel/baytrail: Simplified romstage flow
Change-Id: I99440539d7b7586df66395776dcd0b4f72f66818 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34964 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel')
-rw-r--r--src/soc/intel/baytrail/include/soc/romstage.h7
-rw-r--r--src/soc/intel/baytrail/romstage/Makefile.inc2
-rw-r--r--src/soc/intel/baytrail/romstage/romstage.c59
3 files changed, 11 insertions, 57 deletions
diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h
index ae38b70770..93669f2e61 100644
--- a/src/soc/intel/baytrail/include/soc/romstage.h
+++ b/src/soc/intel/baytrail/include/soc/romstage.h
@@ -24,12 +24,7 @@
#include <arch/cpu.h>
#include <soc/mrc_wrapper.h>
-struct romstage_params {
- struct mrc_params *mrc_params;
-};
-
-void mainboard_romstage_entry_rp(struct romstage_params *params);
-void romstage_common(struct romstage_params *params);
+void mainboard_fill_mrc_params(struct mrc_params *mp);
void raminit(struct mrc_params *mp, int prev_sleep_state);
void gfx_init(void);
diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc
index d43a6fb6e3..2effbb08f6 100644
--- a/src/soc/intel/baytrail/romstage/Makefile.inc
+++ b/src/soc/intel/baytrail/romstage/Makefile.inc
@@ -1,5 +1,7 @@
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
cpu_incs-y += $(obj)/fmap_config.h
+
+romstage-y += ../../../../cpu/intel/car/romstage.c
romstage-y += romstage.c
romstage-y += raminit.c
romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c
diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c
index 80915fdca0..7348d2b08f 100644
--- a/src/soc/intel/baytrail/romstage/romstage.c
+++ b/src/soc/intel/baytrail/romstage/romstage.c
@@ -14,21 +14,16 @@
*/
#include <stddef.h>
-#include <arch/cpu.h>
#include <arch/io.h>
#include <arch/romstage.h>
#include <device/mmio.h>
#include <device/pci_ops.h>
-#include <bootblock_common.h>
#include <console/console.h>
#include <cbmem.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/x86/smm.h>
#if CONFIG(EC_GOOGLE_CHROMEEC)
#include <ec/google/chromeec/ec.h>
#endif
#include <elog.h>
-#include <program_loading.h>
#include <romstage_handoff.h>
#include <string.h>
#include <timestamp.h>
@@ -156,28 +151,12 @@ static int chipset_prev_sleep_state(struct chipset_power_state *ps)
return prev_sleep_state;
}
-/* The cache-as-ram assembly file calls romstage_main() after setting up
- * cache-as-ram. romstage_main() will then call the mainboards's
- * mainboard_romstage_entry() function. That function then calls
- * romstage_common() below. The reason for the back and forth is to provide
- * common entry point from cache-as-ram while still allowing for code sharing.
- * Because we can't use global variables the stack is used for allocations --
- * thus the need to call back and forth. */
-
-static struct postcar_frame early_mtrrs;
-
-/* Entry from cache-as-ram.inc. */
-static void romstage_main(uint64_t tsc)
+/* Entry from cpu/intel/car/romstage.c */
+void mainboard_romstage_entry(void)
{
- struct romstage_params rp = {
- .mrc_params = NULL,
- };
-
- /* Save initial timestamp from bootblock. */
- timestamp_init(tsc);
-
- /* Save romstage begin */
- timestamp_add_now(TS_START_ROMSTAGE);
+ struct chipset_power_state *ps;
+ int prev_sleep_state;
+ struct mrc_params mp;
program_base_addresses();
@@ -196,21 +175,8 @@ static void romstage_main(uint64_t tsc)
gfx_init();
- /* Call into mainboard. */
- mainboard_romstage_entry_rp(&rp);
-
- if (CONFIG(SMM_TSEG))
- smm_list_regions();
-
- prepare_and_run_postcar(&early_mtrrs);
- /* We do not return here. */
-}
-
-/* Entry from the mainboard. */
-void romstage_common(struct romstage_params *params)
-{
- struct chipset_power_state *ps;
- int prev_sleep_state;
+ memset(&mp, 0, sizeof(mp));
+ mainboard_fill_mrc_params(&mp);
timestamp_add_now(TS_BEFORE_INITRAM);
@@ -224,19 +190,10 @@ void romstage_common(struct romstage_params *params)
boot_count_increment();
#endif
-
/* Initialize RAM */
- raminit(params->mrc_params, prev_sleep_state);
+ raminit(&mp, prev_sleep_state);
timestamp_add_now(TS_AFTER_INITRAM);
romstage_handoff_init(prev_sleep_state == ACPI_S3);
}
-
-/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
- * keeping changes in cache_as_ram.S easy to manage.
- */
-asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)
-{
- romstage_main(base_timestamp);
-}