| Age | Commit message (Collapse) | Author |
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Currently coreboot presents the BSP core first, then efficient cores and
Performance cores as indicated below:
```
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3
```
Existing code presents mix of different cores to OS and causes CPU load
balancing and power/performance impact. So, the patch fixes this
disorder by ordering the Performance cores first, compute die efficient
cores next, and finally SOC efficient cores if they are present. This
is done to run the media applications in a power efficient manner,
please refer the ChromeOS patches for details:
https://chromium-review.googlesource.com/c/chromiumos/platform2/+/3963893
BUG=b:262886449
TEST=Verified the code on Rex system
After the fix:
```
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7
```
Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about 20
to 30 ms on brya0.
BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74215
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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coreboot supports three instances of sending EOP:
1. At CSE `.final' device operation
2. Early as with Alder Lake in chip_operations.init if
`SOC_INTEL_CSE_SEND_EOP_EARLY' is selected
3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if
`SOC_INTEL_CSE_SEND_EOP_LATE' is selected
Currently, Alder Lake uses #3 as it results in better and more stable
boot time. However, what would deliver even better result is to not
actively wait for CSE completion.
This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig
which split the action of sending EOP request and receiving EOP
completion response from the CSE.
This patch used in conjunction with #1 can significantly
improves the overall boot time on a Raptor Lake design. For example
`SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36
ms boot time improvement as illustrated below.
| # | Late EOP | Async EOP |
|----------+----------+-----------|
| 1 | 1020.052 | 971.272 |
| 2 | 1015.911 | 971.821 |
| 3 | 1038.415 | 1021.841 |
| 4 | 1020.657 | 993.751 |
| 5 | 1065.128 | 1020.951 |
| 6 | 1037.859 | 1023.326 |
| 7 | 1042.010 | 984.412 |
|----------+----------+-----------|
| Mean | 1034.29 | 998.20 |
| Variance | 4.76 % | 5.21 % |
The improvement is not stable but comparing coreboot and FSP
performance timestamps demonstrate that the slowness is caused by a
lower memory frequency (SaGv point) at early boot which is not an
issue addressed by this patch.
We also observe some improvement on an Alder Lake design. For example,
the same configuration on a kano board can deliver up to 10 ms boot time
improvement as illustrated below.
| # | Late EOP | Async EOP |
|----------+----------+-----------|
| 0 | 1067.719 | 1050.106 |
| 1 | 1058.263 | 1056.836 |
| 2 | 1064.091 | 1056.709 |
| 3 | 1068.614 | 1055.042 |
| 4 | 1065.749 | 1056.732 |
| 5 | 1069.838 | 1057.846 |
| 6 | 1066.897 | 1053.548 |
| 7 | 1060.850 | 1051.911 |
|----------+----------+-----------|
| Mean | 1065.25 | 1054.84 |
The improvement is more limited on kano because a longer PCIe
initialization delays EOP in the Late EOP configuration which make it
faster to complete.
CSME team confirms that:
1. End-Of-Post is a blocking command in the sense that BIOS is
requested to wait for the command completion before loading the OS or
second stage bootloader.
2. The BIOS is not required to actively wait for completion of the
command and can perform other operations in the meantime as long as
they do not involve HECI commands.
On Raptor Lake, coreboot does not send any HECI command after
End-Of-Post. FSP-s code review did not reveal any HECI command being
sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or
`END_OF_FIRMWARE' notifications.
If any HECI send and receive command has been sent the extra code
added in `cse_receive_eop()' should catch it.
According to commit 387ec919d9f7 ("soc/intel/alderlake: Select
SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first
boot after flashing of a Marasov board for instance) request coreboot
to perform a global request out of AFTER_PCI_ENUM notification. Global
request relies on a HECI command. Even though, we tested that it does
not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not
be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent
potential a global reset command to "conflict" with the EOP command.
This patch also introduces a new code logic to detect if CSE is in the
right state to handle the EOP command. Otherwise, it uses the
prescribed method to make the CSE function disable. The typical
scenario is the ChromeOS recovery boot where CSE stays in RO partition
and therefore EOP command should be avoided.
[DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms
[INFO ] HECI: coreboot in recovery mode; found CSE in expected
SOFT TEMP DISABLE state, skipping EOP
[INFO ] Disabling Heci using PMC IPC
[WARN ] HECI: CSE device 16.0 is hidden
[WARN ] HECI: CSE device 16.1 is disabled
[WARN ] HECI: CSE device 16.2 is disabled
[WARN ] HECI: CSE device 16.3 is disabled
[WARN ] HECI: CSE device 16.4 is disabled
[WARN ] HECI: CSE device 16.5 is disabled
BUG=b:276339544
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post sent soon after FSP-s and EOP message receive at
`BS_PAYLOAD_BOOT'. Verify robustness by injecting a
`GET_BOOT_STATE' HECI command with or without `heci_reset'. The
implementation always successfully completed the EOP before
moving to the payload. As expected, the boot time benefit of the
asynchronous solution was under some injection scenario
undermined by this unexpected HECI command.
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I01a56bfe3f6c37ffb5e51a527d9fe74785441c5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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This function calls into `set_feature_ctrl_lock()` to lock
IA32_FEATURE_CONTROL MSRfeature control.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9a03ee6786144dae6fd3a18bcc53cb62919dd42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This function calls into `set_feature_ctrl_vmx_arg()`
to enable VMX for virtualization if not done by FSP (based on
DROP_CPU_FEATURE_PROGRAM_IN_FSP config is enabled) in MeteorLake
SoC based platform.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This function performs locking of the AES-NI enablement state.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch calls into API to disable 3-strike error on
Meteor Lake SoC based platform.
TEST=Able to build and boot google/rex to ChromeOS.
Dumping MSR 0x1A4 shows BIT11 aka 3-strike error is disabled
```
localhost ~ # iotools rdmsr 0 0x1a4
0x0000000000000900
```
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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This patch introduces a new config named
`DROP_CPU_FEATURE_PROGRAM_IN_FSP` to avoid FSP running basic CPU
feature programming on BSP and on APs using the "CpuFeaturesPei.efi"
module.
Most of this feature programming is getting performed today in scope
of coreboot doing MP Init. Running this redundant programming in
scope of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled)
results in CPU exception (for example: attempting to reprogram CPU
feature lock MSR is causing CPU exception).
SoC users should select this config after dropping "CpuFeaturesPei.ffs"
module from FSP-S Firmware Volume (FV). Upon selection, coreboot runs
those additional feature programming on BSP and APs.
This feature is by default enabled, in case of "coreboot running MP
init" aka `MP_SERVICES_PPI_V2_NOOP` config is selected.
At present, this option does not do anything unless any platform
eventually decides to drop FSP feature programming module and choose
coreboot CPU feature programming over it.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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In Intel designs, internal processor errors, such as a processor
instruction retirement watchdog timeout (also known as a 3-strike
timeout) will cause a CATERR assertion and can only be recovered from by
a system reset.
This patch prevents the Three Strike Counter from incrementing (as per
Intel EDS doc: 630094), which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74158
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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Drop devicetree setting X2apic as the same functionality is already
exposed in Kconfig.
To activate X2apic select X2APIC_ONLY or X2APIC_RUNTIME in
the "APIC operation mode".
Note: Your OS must have support for X2APIC. If you are using less
than 256 CPU cores select XAPIC_ONLY here.
Test:
- Booted to OS in X2APIC mode when X2APIC_ONLY or X2APIC_RUNTIME
was selected.
- Booted to OS in XAPIC mode when XAPIC_ONLY was selected.
Change-Id: I65152b0696a45b62a5629fd95801187354c7a93b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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When more than 255 CPU cores are present on a board
the X2APIC must be used.
Select DEFAULT_X2APIC_RUNTIME to support X2APIC by
default when a mainboard enables it in the devicetree.
Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74184
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Inject ACPI code for all generated ASL templates.
This fixes ACPI errors shown in linux when not all sockets
are currently plugged in or some have been disabled.
Test:
Boot Archer City with CONFIG_MAX_SOCKET=4
Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74183
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
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When 'use_rp_mutex' (default = 0) is set in the device tree, a root
port mutex will be added. This mutex is used in _ON and _OFF method,
where the GPIO reset and/or enable GPIO value is changed. The
companion driver, such as WWAN driver, needs to acquire this root
port mutex when accessing the same GPIO pins. Using this common mutex
prevents those invoked methods from being called from different thread
while one is not completed.
An example is that WWAN driver calling _RST method to reset the device
and does remove/rescan for the device while the pm runtime work might
call RTD3 _OFF.
For those root port without additional driver, this mutex is not needed.
BRANCH=firmware-brya-14505.B
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated and _ON and _OFF should use this
mutex.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ibc077528692b2d7076132384fb7bd441be502511
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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This reverts commit e7a1204f26fe3628de99b4ab4e3f32916565b95c.
This initial change was causing a boot failure when transitioning into
recovery mode.
BUG=b:276927816
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas
SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into
recovery mode.
Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74207
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 11f2f88a277124713f7b0023f078fcc2e1a98c32.
Revert initial change as it was causing a boot failure when
transitioning into recovery mode.
BUG=b:276927816
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas
SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into
recovery mode.
Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74206
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table.
990:CSME ROM started execution 0
944:CSE sent 'Boot Stall Done' to PMC 47,000
945:CSE started to handle ICC configuration 225,000 (178,000)
946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0)
947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000)
991:Die Management Unit (DMU) load completed 587,000 (71,000)
0:1st timestamp 597,427 (10,427)
BUG=b:259366109
TEST=Able to see TS elapse prior to IA reset on Rex
Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73713
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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CSE performance data timestamps are different for version 1
Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch
moves the current ADL/RPL timestamp definitions to a separate
header file. It marks current structure as version 1.
BUG=b:259366109
TEST=Boot to OS, check ADL/RPL pre-cpu timestamps.
Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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The Intel Power and Performance (PnP) team requested to update the
following:
- TDC settings for RPL-U 15W variant should be 22A.
- TDC settings for RPL-P 28W variant should be 33A.
BUG=b:275694022
BRANCH=firmware-brya-14505.B
TEST=PnP validated performance impact with these settings on both
RPL-U 15W and RPL-P 28W
Change-Id: I1141414785a990b975e32ebc03e490b83082aab7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74046
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The patch defines acpi_set_cpu_apicid_order() which orders the APIC IDs
based on APIC IDs of Performance cores and Efficient cores, calculates
the total core count and total Performance cores count, populates the
information in the cpu_apicid_order_info struct.
The helper function useful to present the Performance and Efficient
cores in order to OS through MADT table and _CPC object.
TEST=Verify the build for Gimble (Alder Lake board)
Change-Id: I8ab6053ffd036185d74d5469fbdf36d48e0021ce
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72131
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to document 640858 MTL EDS Vol2, bit 18 (PWR_PERF_PLATFRM_OVR) of MSR_POWER_CTL must be set.
This patch is backported from
`commit 117770d32468e63df ("soc/intel/
alderlake: Enable Energy/Performance Bias control")`.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic83225b619c49db0b49b521a83a2f1dc1ad69be8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74155
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.
This patch is backported from
`commit 0bb2225718ef898c ("soc/intel/alderlake: Add EPP override
support")`.
BUG=b:266522659
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8172276159fe3987dae36ec30ebceb76dd0ef326
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74154
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the 28W TDP version of the ADL-P with MCHID 0x4629.
Verified that all 28W SoCs have the same PL1/PL2 defined
in Intel document #655258 "12th Generation Intel Core
Processors Datasheet, Volume 1 of 2".
Fixes the error seen in coreboot log:
[ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration
Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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Add ACPI support for Sapphire Rapids. Passes FWTS ACPI tests.
The code was written from scratch because there are Xeon-SP specific
implementation especially Integrated Input/Output (IIO).
Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71967
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Intel FSP has "debug" build which is not public, used for debugging by
approved developers. Add a Kconfig to indicate that coreboot is building
with debug version of FSP so we can adjust few things (i.e. flash
layout) in the case.
BUG=b:262868089
TEST=Able to build and boot google/rex.
Change-Id: I5555a2ab4182ad0036c42be6fea3d934ffd0db8c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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PortUsb30Enable has been overridden unexpectedly, this patch fixed it.
BUG=b:276181378
Test=boot to rex and check USB3 ports are working.
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ic04b9eb236ed28a76ee516c52fc0c983cb8f2c0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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The patch enables addition of core_type member to 'struct cpu_info'
for MeteorLake platform.
TEST=Build and verify the code for Rex
Change-Id: I01abed6b87bec2f8eb39bfc941faff070b83abe6
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74130
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about 20
to 30 ms on brya0.
BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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coreboot supports three instances of sending EOP:
1. At CSE `.final' device operation
2. Early as with Alder Lake in chip_operations.init if
`SOC_INTEL_CSE_SEND_EOP_EARLY' is selected
3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if
`SOC_INTEL_CSE_SEND_EOP_LATE' is selected
Currently, Alder Lake uses #3 as it results in better and more stable
boot time. However, what would deliver even better result is to not
actively wait for CSE completion.
This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig
which split the action of sending EOP request and receiving EOP
completion response from the CSE.
This patch used in conjunction with #1 can significantly
improves the overall boot time on a Raptor Lake design. For example
`SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36
ms boot time improvement as illustrated below.
| # | Late EOP | Async EOP |
|----------+----------+-----------|
| 1 | 1020.052 | 971.272 |
| 2 | 1015.911 | 971.821 |
| 3 | 1038.415 | 1021.841 |
| 4 | 1020.657 | 993.751 |
| 5 | 1065.128 | 1020.951 |
| 6 | 1037.859 | 1023.326 |
| 7 | 1042.010 | 984.412 |
|----------+----------+-----------|
| Mean | 1034.29 | 998.20 |
| Variance | 4.76 % | 5.21 % |
The improvement is not stable but comparing coreboot and FSP
performance timestamps demonstrate that the slowness is caused by a
lower memory frequency (SaGv point) at early boot which is not an
issue addressed by this patch.
We also observe some improvement on an Alder Lake design. For example,
the same configuration on a kano board can deliver up to 10 ms boot time
improvement as illustrated below.
| # | Late EOP | Async EOP |
|----------+----------+-----------|
| 0 | 1067.719 | 1050.106 |
| 1 | 1058.263 | 1056.836 |
| 2 | 1064.091 | 1056.709 |
| 3 | 1068.614 | 1055.042 |
| 4 | 1065.749 | 1056.732 |
| 5 | 1069.838 | 1057.846 |
| 6 | 1066.897 | 1053.548 |
| 7 | 1060.850 | 1051.911 |
|----------+----------+-----------|
| Mean | 1065.25 | 1054.84 |
The improvement is more limited on kano because a longer PCIe
initialization delays EOP in the Late EOP configuration which make it
faster to complete.
CSME team confirms that:
1. End-Of-Post is a blocking command in the sense that BIOS is
requested to wait for the command completion before loading the OS or
second stage bootloader.
2. The BIOS is not required to actively wait for completion of the
command and can perform other operations in the meantime as long as
they do not involve HECI commands.
On Raptor Lake, coreboot does not send any HECI command after
End-Of-Post. FSP-s code review did not reveal any HECI command being
sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or
`END_OF_FIRMWARE' notifications.
If any HECI send and receive command has been sent the extra code
added in `cse_receive_eop()' should catch it.
According to commit 387ec919d9f7 ("soc/intel/alderlake: Select
SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first
boot after flashing of a Marasov board for instance) request coreboot
to perform a global request out of AFTER_PCI_ENUM notification. Global
request relies on a HECI command. Even though, we tested that it does
not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not
be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent
potential a global reset command to "conflict" with the EOP command.
BUG=b:276339544
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post sent soon after FSP-s and EOP message receive at
`BS_PAYLOAD_BOOT'. Verify robustness by injecting a
`GET_BOOT_STATE' HECI command with or without `heci_reset'. The
implementation always successfully completed the EOP before
moving to the payload. As expected, the boot time benefit of the
asynchronous solution was under some injection scenario
undermined by this unexpected HECI command.
Change-Id: Ib09dcf9140eb8a00807a09e2af711021df4b416f
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73619
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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The patch enables addition of core_type member to 'struct cpu_info' for
Alderlake platform.
TEST=Build and verify the code for Gimble
Change-Id: Ia065b98c2013e78328fd38bed9c667792d6d1f4d
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74089
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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The patch adds new member 'core_type' to the 'struct apic_path' and
updates core type information.
TEST=Build the code for MTL
Change-Id: I1d34068fd5ef43f8408301bf3effa9febf85f683
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74088
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch avoids the redundant programming of SRAM BAR when
the SRAM PCI device is enabled. Rather read the PCH SRAM Base
Address Register while enabling crashlog feature.
Additionally, this patch relies on PCI enumeration to get the
SRAM BAR rather than hijacking the SPI temporary base address
which might have resulted in problems if SPI is disabled on
some platform with BAR being implemented.
TEST=Able to build and boot google/marasov and crashlog is working.
Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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From Meteor Lake onwards Intel FSP will generate the Trace Hub related
HOB if the Trace Hub is configured to save data in DRAM. This memory
region is used by Trace Hub to store the traces for debugging purpose.
This driver locates the HOB and marks the memory region reserved so
that OS does not use it.
Intel Trace Hub developer manual can be found via document #671536 on
Intel's website.
Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
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This patch adds a check for zero based SRAM base address. It will
help to avoid running into problems if the SRAM is disabled and
the base address register is zero.
TEST=Able to build and boot google/marasov with PCH SRAM being
disabled.
Change-Id: Iebc9dc0d0851d5f83115f966bf3c7aad1eb6bc01
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change to use simple device function for setting PMAX_LOCK because
the Sapphire Rapids PCU device is not scanned during coreboot PCIe
bus scan and would see "PCI: dev is NULL!" failure.
Change-Id: I3156a6adf874b324b5f4ff5857c40002220e47ab
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72400
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This patch moves USB Port Status and Control (PORTSC) Reg definition
into IA common code to allow other SoC code to reuse it without
redefining the same for each SoC.
TEST=Able to build and boot google/taeko where USB wake is working.
Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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For some Xeon-SP (such as SPR-SP), more buses should be probed.
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
|
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Add support for Intel SPR-SP to uncore_acpi.c.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com>
Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
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For SPR-SP, the SMM_FEATURE_CONTROL register is in UBOX_URACU_FUNC
instead of UBOX_DEV_PMON.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ide46c5f9cdf65b7e05552449b08ad4d7246664cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
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Add platform cpu info for known microcode, print cpuid & processor
branding string. This will print as in the following example:
CPU: Intel(R) Xeon(R) Platinum 8468H
CPU: ID 806f6, Sapphire Rapids E3, ucode: 2b000130
CPU: AES supported, TXT supported, VT supported
Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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FSP may program a different ID under certain circumstances.
Read IOAPIC ID from hardware instead of using some define that
might not reflect how hardware is configured.
Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Having these two functions public allow "asynchronous"
HECI command implementation.
Typically, these function can be use to implement an asynchronous
End-Of-Post.
BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Successful compilation for brya0
Change-Id: I7d029bb9af4b53f219018e459d17df9c1bd33fc1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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The default SPD size is set to 256 bytes, instead of 512 for
LPDDR4/DDR4 if not overridden by the mainboard Kconfig. This caused
the SMBus libraries to read only the lower half of the DIMM SPD on
protectli/vault_ehl. The lower half of the SPD passed to FSP causes
a bug in DIMM change detection, which relies on the CRC of the
manufacturer bytes in the upper half of the SPD (CRC of zero bytes
always gives zero so no change was assumed). Setting the DIMM SPD size
to 512 fixes it.
Setting the SPD size in SoC will also avoid such problems in the future
Elkhart Lake ports. Elkhart Lake supports only LPDDR4/DDR4 so providing
the correct default of 512 bytes is an obvious thing to do.
TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see
FSP is retraining the memory instead of doing the fastboot with old
DIMM data.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I998ed8781951034419cadc26c04ff1e0a124b267
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73933
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This patch renames all references of `top_of_ram` (TOM) in IA common
`basecode` module (for example: functions, variables, Kconfig,
Makefile and comments) with `ramtop` aka top_of_ram to make it more
meaningful and to avoid conflicts with Intel SA chipset TOM registers.
BUG=Able to build and boot google/rex with the same ~49ms savings
in place.
Change-Id: Icfe6300a8e4c5761064537fb256cfecbe2afb2d8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73881
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To be consistent with other occurrences in soc/intel/common, remove the
return statements of weak void funtions since they are not generally
useful.
Found by the linter.
Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Change-Id: I3fb8217cfcae65b5dc317458b59aa431f1ccdaef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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If the host supports CXL, get proximity domain info from FSP HOB. The
proximity domains may include both processor domains and CXL domains.
Add header definition for proximity domain.
Add CXL memory into memory map.
Change-Id: If3f856958a3e6ed3909240ee455bb639e487087f
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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DPR should not be configured for VTD devices of other stacks for
SPR-SP. Such processor(s) would be configured with
SOC_INTEL_MMAPVTD_ONLY_FOR_DPR.
Change-Id: Ib33b1b62f59a10d362c6585b1403490d4a1aedeb
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72616
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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... instead of ME base/limit if the processor is configured with
SOC_INTEL_HAS_NCMEM.
Change-Id: I95783cad1a2d5a3599d120ea0c98e2aa8703bdb4
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72615
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
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This soc utility function can set cmos flag to enforce
FSP MRC training.
Change-Id: I88004cbfdcbe8870726493576dfc31de4b6036a9
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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After calling FSP MemoryInit API, if there is an error, some FSPs
(such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB.
Check existence of such a HOB and handle it accordingly.
Change-Id: Icb5c31daa223ba6b06ba1b2de4f8808e0b27899e
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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The Kconfig help section says FSP uses 192 KiB of stack (0x30000) and
coreboot's romstage requires ~1 KiB, but it is not satisfied currently.
Increase the BSP stack size by the missing 1KiB for romstage like
other SoCs do.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iddd4a4613bc174aec4331732371a27450225258c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73820
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Commit 6a6ac1e0b929 ("arch/x86/cpu: introduce and use
device_match_mask") added the device_match_mask element to the
cpu_device_id struct and uses it to be able to mask off for example the
stepping ID when checking for CPU table entry that matches the silicon
the code is running on. Commit 3ed903fda9cb ("soc/intel/xeon_sp/spr: Add
Sapphire Rapids ramstage code") added a CPU table that was missing the
device_match_mask which results in this being 0, so the first entry of
the CPU table would match for any Intel CPU which isn't the intended
behavior. Also use CPU_TABLE_END instead of the final {0, 0, 0} array
element.
Likely all entries could be replaced by one entry that uses the
CPUID_ALL_STEPPINGS_MASK instead of the CPUID_EXACT_MATCH_MASK, but
that's out of scope for this fix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib0be2e9fe3c31487c83c9b1cf305a985416760b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Programming MTRR happens later in the
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT codepath.
fast_spi_cache_bios_region() assumes an existing MTRR solution from
x86_setup_mtrrs_with_detect().
This fixes a problem introduced by 829e8e6 "soc/intel: Use common
codeflow for MP init".
Change-Id: I9b6130cf76317440ebe7a7a53e460e2b658d198e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73836
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace the legacy ACPI Processor() object as it only
supports 8bit IDs and thus no more than 255 cores. Use the
new ACPI Device() object that supports more than 255 cores.
Test:
- Observed no ACPI errors on IBM/SBP1 and Linux 5.15 running
384 CPU cores in total.
- Verified on Intel ADL RVP with 20 cores that Linux 5.15 is
still working without errors.
Change-Id: I309c06b6824704c84fd16534655334a6f269904a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73578
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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In cases where there are limitations on the connected device behind the
PCIe root port it can be necessary to limit the speed. The FSP parameter
'PcieRpPcieSpeed' allows to set the speed limit.
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: I9fc24de1682279e4ae4c090147a6ef7995b441bc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
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Add the AlderLake-P 4+4+2 (28W) with MCH_ID 0x4629 to the
vr_config table.
Change-Id: I606ef429f47dfe386177f7257b153acc1611bb61
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be
configured with non-zero IOSSTATE values.
TEST=Able to build and boot google/rex. GPIO debug print is showing
GPIO PAD config DW1 bit[14:17] are getting programmed.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e63fe946d541769fa0ddbb23f902f9c905735c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Intel SPR-SP chipset has EBG instead of LBG.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: I9429fe332bb5f01a41aa205c76ad9f0159f93eee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71959
Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com>
Reviewed-by: TimLiu-SMCI <timliu@supermicro.com.tw>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It implements SPR ramstage including silicon initialization, MSR
programming, MP init and certain registers locking before booting
to payload.
Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Several FSP HOBs processing codes are similar to Intel Cooperlake-SP
codes in soc/intel/xeon_sp/cpx.
Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246
and Emmitsburg PCH EDS Doc#606161.
Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This patch modifies the serial msg log_level at runtime to highlight
an ERROR if the DIMM count is zero. It would help to draw the
attention while parsing the serial msg and catch any underlying issue.
TEST=Able to see ERROR msg while booting google/rex with FSP v3064
Without this patch:
[DEBUG] 0 DIMMs found
With this patch:
[ERROR] No DIMMs found
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iacf41efecb4962f91cf322bbc50636dc44033e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73756
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some MSRs used in SPR code are common among currently supported
Xeon-SP generations and are added to the top-level Xeon-SP msr.h. MSRs
which have changed are added to SPR's soc_msr.h.
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Change-Id: I92b433a9686734716dc7936895fb79c7751f7f9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
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Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Change-Id: I2ecfebdde453a48b7b0e6f21b3c4394411eed671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
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Change-Id: I2ece7aac4339266068d4fc8fb1c58d0573eb2895
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe
the I/O devices like USB and NVMe fail to enumerate in UEFI
Payload (basically proving that DMA protection works).
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iecaa3d04f1447b7e73507ca57a0d23d42e24d663
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68450
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The HSPHY firmware must be downloaded to DMA-allowed host address
space. Check for DMA buffer presence and use it as the buffer for HSPHY
firmware to be downloaded from CSME.
TEST=Successfully load HSPHY firmware to CPU on MSI PRO Z690-A DDR4
with DMA protection enabled.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68556
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I226305fa547e9d9ea541a5806d543aa358bce28d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72069
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add new common block with VT-d/IOMMU support. The patch adds an
option to enable DMA protection with PMR. However the payload and
OS must support VT-d in order to properly handle I/O devices.
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe
the I/O devices like USB and NVMe fail to enumerate in UEFI
Payload (basically proving that DMA protection works).
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
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With newer xeon_sp processors, the concept of "north bridge" became
obsolete, instead uncore should be used. Therefore we use uncore_acpi.c
(instead of nb_acpi.c) going forward.
Change-Id: I91ec9023152996bf9f2300a369aff3c4f19d75fd
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
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This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I8f8a0bfeaea508d3b4ad1b3fe2e68742cbab5570
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73687
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Icd3d16ab2cb34dc81fc12ec139c52ecaa170528d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73686
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I1fe6072a3c23a02c9a691406f179bfc8f0f18a93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Intel Meteor Lake decides to enable early caching of the TOM region to
optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_TOM`
config.
TEST=Able to build and boot google/rex to ChromeOS and reduce the boot
time by 77 ms.
Without this patch:
950:calling FspMemoryInit 936,811 (19,941)
951:returning from FspMemoryInit 1,041,935 (105,123)
With this patch:
950:calling FspMemoryInit 905,108 (20,103)
951:returning from FspMemoryInit 964,038 (59,929)
Change-Id: Iebb3485b052386b43d5bccd67a04e6115cbcc20d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73274
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch uses the IA common code API to store the top_of_ram (TOM)
address intonon-volatile space (CMOS).
The code logic will update the TOM address in CMOS NVS if the
`top_of_ram` address is calculated differently in any boot and
also takes care of caching the updated range.
TEST=Able to build and boot google/rex to ChromeOS.
First boot:
Before calling into FSP-M
[DEBUG] 0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB
[DEBUG] 0x00003ffffff80800: PHYMASK0: Length = 0x0000000000080000, Valid
[DEBUG] 0x00000000fef80006: PHYBASE1: Address = 0x00000000fef80000, WB
[DEBUG] 0x00003ffffffc0800: PHYMASK1: Length = 0x0000000000040000, Valid
[DEBUG] 0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP
[DEBUG] 0x00003fffff000800: PHYMASK2: Length = 0x0000000001000000, Valid
[DEBUG] 0x00000000f9800005: PHYBASE3: Address = 0x00000000f9800000, WP
[DEBUG] 0x00003fffff800800: PHYMASK3: Length = 0x0000000000800000, Valid
...
[DEBUG] tom_table invalid signature
[DEBUG] top_of_ram = 0x76000000
[DEBUG] Updated the TOM address into CMOS 0x76000000
On consecutive boot:Before calling into FSP-M:
The TOM region is already cached.
[DEBUG] 0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB
[DEBUG] 0x00003ffffff80800: PHYMASK0: Length = 0x0000000000080000, Valid
[DEBUG] 0x00000000fef80006: PHYBASE1: Address = 0x00000000fef80000, WB
[DEBUG] 0x00003ffffffc0800: PHYMASK1: Length = 0x0000000000040000, Valid
[DEBUG] 0x00000000ff000005: PHYBASE2: Address = 0x00000000ff000000, WP
[DEBUG] 0x00003fffff000800: PHYMASK2: Length = 0x0000000001000000, Valid
[DEBUG] 0x00000000f9800005: PHYBASE3: Address = 0x00000000f9800000, WP
[DEBUG] 0x00003fffff800800: PHYMASK3: Length = 0x0000000000800000, Valid
[DEBUG] 0x0000000075000005: PHYBASE4: Address = 0x0000000075000000, WP
[DEBUG] 0x00003fffff000800: PHYMASK4: Length = 0x0000000001000000, Valid
Change-Id: I2569495570652c488096f6a29f58dd8f0103af9d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73273
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch implements a module that can store the top_of_ram (TOM)
address into non-volatile space (CMOS) during the first boot and
use it across all consecutive boot.
As top_of_ram address is not known until FSP-M has exited, it
results into lacking of MTRR programming to cache the 16 MB TOM,
hence accessing that range during FSP-M and/or late romstage causing
long access times.
Purpose of this driver code is to cache the TOM (with a fixed size of
16MB) for all consecutive boots even before calling into the FSP.
Otherwise, this range remains un-cached until postcar boot stage
updates the MTRR programming. FSP-M and late romstage uses this
uncached TOM range for various purposes (like relocating services
between SPI mapped cached memory to DRAM based uncache memory) hence
having the ability to cache this range beforehand would help to
optimize the boot time (more than 50ms as applicable).
TEST=Able to build and boot google/rex to ChromeOS.
Without this patch:
950:calling FspMemoryInit 936,811 (19,941)
951:returning from FspMemoryInit 1,041,935 (105,123)
With this patch:
950:calling FspMemoryInit 905,108 (20,103)
951:returning from FspMemoryInit 987,038 (81,929)
Change-Id: I29d3e1df91c6057280bdf7fb6a4a356db31a408f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73272
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This patch selects `X86_CLFLUSH_CAR` config for running
`clflush` to invalidate the cache region.
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6b2dce39f82e28cd99ad8621c78bae494c4f16ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73333
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Set up SRAT table in X2APIC mode when necessary.
Change-Id: Ib8b4cebefe81f7b5514524dba2fa364eee4bb157
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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For Intel SPR-SP, the SAD device is hidden, so pcidev_path_on_bus()
returns NULL. Therefore use pci_s_write_config32() instead.
Move lock_pam0123() from finalize.c to util.c, to be together with
unlock_pam_regions().
Change-Id: Ib08d423d8c4d482612077b66dab3878018da8f2b
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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Intel SPR-SP has its specific way to get the bus number of ubox.
Move the current implementations to CPX-SP and SKX-SP folders.
Change-Id: I2b69be74d140115f9f78bc991fb690e3c90c88db
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
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This fixes the case where a Broadwell CPU is combined with an AMD or
NVIDIA GPU would result in using the Broadwell GPU VBIOS file from CBFS
for the discrete GPU too. A further improvement would be to use a list
of the Intel iGPU PCI IDs like it is done in the Skylake code.
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3eb50cb9a0539255d50e5cd8163f10c3a062cc4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73611
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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This patch updates PMC API name from `pmc_send_pci_enum_done` to
`pmc_send_bios_reset_pci_enum_done` to inform PMC IPC about BIOS done
is also set along with PMC enumeration being done.
BUG=b:270942083
TEST=Able to build and boot google/rex.
Change-Id: I1cf8cb1ecadeb68c109be6b0e751a3f2c448ae4f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
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Change-Id: I13ed156a1b967e87fa30b1867feed03c3d17b992
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: David Hendricks <ddaveh@amazon.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
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Raptor Lake i9 CPUs have 8P+16E cores for a total of 32 threads.
Change-Id: I26a729a585e7dc14f38c9092056eb0280726f053
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73514
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Hook up microcode from 3rdparty repo for:
- 06-ba-02 (CPUID signature: 0xb06a2)
Change-Id: Icb2fc9350ebc33ef150f1ab5df1006ed956478d6
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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On platforms with more than 255 cores the ACPI CPU string
would overflow and generate duplicates. Fix that by changing
the string to hex and use 3 digits.
Test:
Able to boot without ACPI errors on IBM/SBP1 which has
384 actives cores.
Change-Id: I1887928da0c049c27e2ec129f49051b24048b33b
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
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Fixes detection of the on-board RAM (Samsung K4AAG165WA-BCWE) on the
System76 Lemur Pro 11 (lemp11).
Change-Id: Ibe56c0f2b81d660303429cd2e21a7bb6cd433da5
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
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Align support for enable wake-on-usb attach/detach as was
introduced in Cannon Lake in commit 811284125f0a
("soc/intel/cannonlake: Add UWES ASL into xhci.asl").
This adds the USB Wake Enable Setup (UWES) ASL blocks
required to inform the OS about plug wake events bits
being set in the PORTSCN register configured by devicetree.
BUG=b:230398487
BRANCH=none
TEST=Verify USB-A device could wake up Moli.
Signed-off-by: Scott Chao <Scott_Chao@wistron.com>
Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73173
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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On the 4 socket IBM/SBP1 platform with 384 cores lots
of space for ACPI tables is required.
Bump MAX_ACPI_TABLE_SIZE_KB to 400 to fix CBMEM corruption.
Change-Id: Ifbd79e84097231b41f900425a2e8750dce71a25a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Hook up microcode from 3rdparty repo for:
- 06-b7-01 (CPUID signature: 0xb0671)
Verified microcode blob was in CBFS on Clevo PD50SNE (system76/serw13),
which has an i9-13900HX.
Change-Id: If91ff9233a5e1dd1db76edf33a76c55f5dddc9b4
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Server platform doesn't have S4 state so select DISABLE_ACPI_HIBERNATE
to remove S4 state from available sleepstates.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ie5ddb1a98cd5bbd854b915c93694d1ebcb9bddd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
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The comment that the PchHdaAudioLink UPDs only configure GPIOs is
incorrect. Setting this GPIO to 1 or 0 will not change the HDA
GPIO configuration; it will make the sound work when set to 1,
or not work when set to 0.
Remove the incorrect comment and make the UPD configurable from the
devicetree.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with
the D3COLD_SUPPORT symbol, as it allows for more granular control.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Select `HAVE_HYPERTHREADING` and hook up the hyper-threading setting
from the FSP to the option API so that related mainboards don't have to
do that. Unless otherwise configured (e.g. the CMOS setting or
overridden by the mainboard code), the value from the Kconfig setting
`FSP_HYPERTHREADING` is used.
Port of commit a182faeb88a0 ("soc/intel/alderlake: Hook up FSP hyper-threading setting to option API")
Change-Id: I0b3e1a4049312c6b1ec950382c92274e0350001f
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This commit separates setting FSP debug params from the rest of code and
configures FSP serial port parameters. Other ports (0x3E8 and 0x2E8)
are omitted since Elkhart Lake FSP only supports 0x3F8 and 0x2F8.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I84f7c19a7c2fd5a4db18f5a37e1c667da017aace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Move 'asmlinkage' before the function type for consistency.
Change-Id: I293590ef917b78c6ed3d151cd0080e42d0f10651
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73259
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I42856424d3b55107f1758fb05f7ddbee3550d8b2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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This patch optimizes CPU MP Init related configs being used within
multiple SoC directory and moving essential configs into common code
to let the SoC user to choose as per the requirement.
TEST=Able to build and boot google/kano and google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I12adcc04e84244656a0d2dcf97607bd036320887
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Elkhartlake based SoCs uses Intel's Management Engine (ME), version 15.
This patch selects ME 15 specification defined at common code and
removes elkhartlake SoC specific ME code and data structures.
BUG=b:260309647
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I3186f509c63b3a892c72cb1fa08fc094735d6eeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73245
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Alderlake based SoCs uses Intel's Management Engine (ME), version 16.
This patch selects ME 16 specification defined at common code and
removes alderlake SoC specific ME code and data structures.
BUG=b:260309647
Test=Build verified for brya.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ib94e4662c735b1c31c8dfca1cfa881e6fa4070fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73244
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Cannonlake based SoCs uses Intel's Management Engine (ME), version 12.
This patch selects ME 12 specification defined at common code and
removes cannonlake SoC specific ME code and data structures.
BUG=b:260309647
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ifc64cf63736bb730492b1732a22669a0415816a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73140
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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