diff options
| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-13 14:59:36 +0100 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2023-03-15 14:44:24 +0000 |
| commit | 742b65bdf6e0fc6dd46b30c8c91eae5d1efff828 (patch) | |
| tree | 39586814a3e5a74b79e5fdf0431b0869b3d278cf /src/soc/intel | |
| parent | 41546a524091165d04f0a91bba431f3245877bf2 (diff) | |
soc/intel/tigerlake: Select `X86_CLFLUSH_CAR` config
This patch selects `X86_CLFLUSH_CAR` config for running `clflush`
to invalidate the cache region based on commit 3134a81 for boot
performance improvement.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/tigerlake/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index d4b16c0d93..84425cc6e3 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -95,6 +95,7 @@ config CPU_SPECIFIC_OPTIONS select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50 + select X86_CLFLUSH_CAR config MAX_CPUS int |