diff options
| author | Ivy Jian <ivy.jian@quanta.corp-partner.google.com> | 2023-03-31 17:56:11 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-04-01 06:07:18 +0000 |
| commit | c5c6372395ece2c8a376e284f2c215e1d2738307 (patch) | |
| tree | 2139be08fc11954e43e79b664e3fed1123599059 /src/soc/intel | |
| parent | 2afac1956f672fb8dad61a3ef5f0f97b6d8aadb7 (diff) | |
soc/intel/meteorlake: Fix PortUsb30Enable configuration
PortUsb30Enable has been overridden unexpectedly, this patch fixed it.
BUG=b:276181378
Test=boot to rex and check USB3 ports are working.
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ic04b9eb236ed28a76ee516c52fc0c983cb8f2c0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel')
| -rw-r--r-- | src/soc/intel/meteorlake/fsp_params.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 041429dcc4..d345f1b27d 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -487,7 +487,6 @@ static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, max_port = get_max_tcss_port(); for (i = 0; i < max_port; i++) { - s_cfg->PortUsb30Enable[i] = config->tcss_ports[i].enable; if (config->tcss_ports[i].enable) s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; } |