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2023-04-15soc/intel/cmn/cse: Move API to get FW partition info into cse_lite.cSubrata Banik
The patch moves API that gets the CSE FW partition information into CSE Lite specific file aka cse_lite.c because the consumer of this API is the cse_lite specific ChromeOS devices hence, it's meaningful to move the cse lite specific implementation inside cse_lite.c file. BUG=b:273661726 TEST=Able to build and boot google/marasov with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I49ffaec467f6fb24327de3b2882e37bf31eeb7cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/74382 Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15soc/intel/tigerlake: Enable early caching of RAMTOP regionLean Sheng Tan
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73738 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15soc/intel/alderlake: Enable early caching of RAMTOP regionLean Sheng Tan
Enable early caching of the TOM region to optimize the boot time by selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config. Purpose of this feature is to cache the TOM (with a fixed size of 16MB) for all consecutive boots even before calling into the FSP. Otherwise, this range remains un-cached until postcar boot stage updates the MTRR programming. FSP-M and late romstage uses this uncached TOM range for various purposes (like relocating services between SPI mapped cached memory to DRAM based uncache memory) hence having the ability to cache this range beforehand would help to optimize the boot time (more than 50ms as applicable). TEST=Able to build and boot Starlab ADL laptop to OS. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73736 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-15soc/intel/meteorlake: Add B0 stepping CPU IDMusse Abdullahi
This patch adds CPU ID for B0 stepping (aka ES2). DOC=#723567 TEST=Able to boot on B0 rvp and get correct CPU Name in coreboot log. Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184 Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74300 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15soc/intel/baytrail: Make acpi_madt_irq_overrides() staticKyösti Mälkki
Change-Id: Id362e023358054df2c4511fd108c313da868306d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74325 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPICKyösti Mälkki
Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have special handling for the time being. Change of aopen/dxplplusu is coupled with sb/intel/i82801dx. Change of emulation/qemu-i440fx is coupled with intel/i82371eb. For asus/p2b, this adds MADT LAPIC entries, even though platform has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates the MADT, including an entry for LAPIC address. Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-14cpu,soc/intel: Use acpigen_write_processor_device()Elyes Haouas
Use acpigen_write_processor_device() instead of deprecated acpigen_write_processor(). Change-Id: I1448e0a8845b3a1beee0a3ed744358944faf66d8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72488 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_configLean Sheng Tan
This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB that was caused by the API change in commit 36e6f9bc047f86e1628c8c41d3ac16d80fb344de. This patch removes the broken API function and also adds package_id log print same as previous commit mentioned above. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74436 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-14soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)Subrata Banik
This patch avoids cannonlake base config to select eNEM for CAR by default. Rather allow other SoC config to choose the applicable CAR mode between eNEM and NEM. CML and WHL select eNEM whereas CFL decided to use NEM for CAR setup. Here is some background about why CFL SoC platform decided to choose NEM over eNEM: It was found that some coffeelake CPUs like Intel i3 9100E fail to enter CAR mode because some MSR used by NEM enhanced are lacking. According to the Intel SDM CPUID.EAX=07h.ECX=0 reg EBX[12 or 15] should indicate the presence of IA32_PAR_ASSOC and CPUID.EAX=10h.ECX[1 or 2] reg ECX[2] should indicate IA32_L3_QOS_CFG and IA32_L2_QOS_CFG respectively but even on a Intel coffeelake CPU that works with the NEM_ENHANCED these CPUID bits are all 0 so there is no way of knowing whether NEM_ENHANCED will work at runtime. Instead just always use regular NEM. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14soc/intel/xeon_sp: Don't sort struct device cpus for numaArthur Heymans
Currently the xeon_sp code reassigns struct devices apic_id so that srat entries can be added in a certain order. This is not a good idea as it breaks thread local storage which contains a pointer to its struct device cpu. This moves the sorting of the lapic_ids to the srat table generation and adds the numa node id in each core init entry. Now it is done in parallel too as a bonus. Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68912 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14soc/intel/meteorlake: Replace assert with error messageKapil Porwal
Avoid asserts related to CNVi UPDs which are not boot critical. Instead, add error messages which are more helpful in identifying the issue. BUG=none TEST=Boot to the OS on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I49a988b7eda009456d438ba7be0d2918826e1c36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74370 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-14soc/intel/common: Fix acpigen use for processor DeviceKyösti Mälkki
Change-Id: Ib4e21732ac31076a1a97a774e03c8466d17c5f29 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-13soc/intel/cmd/block: Implement an API to get firmware partition detailsDinesh Gehlot
This patch retrieves details of a specified firmware partition table. The information retrieved includes the current firmware version and other information about the firmware partition. The patch communicates with the ME using the HECI command to acquire this information. BUG=b:273661726 Test=Verified the changes for ISH partition on nissa board. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74005 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-04-13soc/intel/meteorlake: Hook up UPD CnviWifiCoreKapil Porwal
Hook the newly created/exposed CnviWifiCore UPD up as a chip driver. Enable this option by default to maintain the existing behavior. BUG=b:270985197 TEST=Verified by enabling/disabling the UPD on google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I5b4662c2a064f7c9074797c8a2541dcf1dd686fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/74306 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13soc/intel/common: Update cpu_apic_info_type structSridhar Siricilla
The patch updates total cpu count variable and total P-core count in cpu_apic_info_type structure to `unsigned short int` to address more cores. TEST=Verify the build on Rex Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I46239cc7ad9870e7134955af56b9f6625be2b002 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-13soc/intel/xeon_sp: Fix very small total memory when CXL is enabledJohnny Lin
Processor attached memory should not use reserved_ram_from_to and treat the calculation of gi_mem_size size as 64MB. By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms, this should fix small total memory issue. Before the fix running command 'free -g -h' under Linux shows the total memory is only 1.4Gi, after the fix it's showing the expected total memory size 15Gi. Tested=On AC without attaching CXL memory, the total memory size is the same as de-selecting SOC_INTEL_HAS_CXL. On OCP Crater Lake with CXL memory attached, CXL memory can be recognized in NUMA node 1: numactl -H available: 2 nodes (0-1) node 0 cpus: 0 1 2 3 4 5 6 .. 59 node 0 size: 95854 MB node 0 free: 93860 MB node 1 cpus: node 1 size: 63488 MB node 1 free: 63488 MB node distances: node 0 1 0: 10 14 1: 14 10 Change-Id: I38e9d138fd284620ac616a65f444e943f1774869 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74296 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-12Revert "soc/intel/rtd3: Hook up supported states to Kconfig"Michael Niewöhner
This reverts commit dbb97c3243e55a0fd00e692d150c9d38d09b57af. Reason for revert: dependency for revert CB:73903 Change-Id: Ibc81483239a13f456d20631725641b7219af4ef8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73904 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"Michael Niewöhner
This reverts commit 6bfca1b689e48be4f72e8fa401f3558d845fc282. Reason for revert: dependency for revert CB:73903 Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol"Michael Niewöhner
This reverts commit fd4ad29f1824ad5d8df67f3e30d3908d24cbd8a4. Reason for revert: dependency for revert CB:73903 Change-Id: I5ed5e3e267032d62d65aef7fb246a075dccc9cf6 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12soc/intel/xeon_sp: Drop Kconfig MAX_SOCKET_UPDPatrick Rudolph
The Kconfig is only used in common code to gather the build time maximum socket number FSP support. The same information is available in FSP header as MAX_SOCKET, thus use the FSP as truth of source. Currently MAX_SOCKET is 4. Change-Id: I10282c79dbf5d612c37b7e45b900af105bb83c36 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74339 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11ACPI: Add helper for MADT LAPICsKyösti Mälkki
This avoids some code duplication related to X2APIC mode. Change-Id: I592c69e0f52687924fe41189b082c86913999136 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11ACPI: Add helper for MADT LAPIC NMIsKyösti Mälkki
This avoids some code duplication related to X2APIC mode. Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hiddenMichał Żygowski
Set the P2SB device as hidden as FSP-S is hiding the PCI configuration space from coreboot on Alder Lake systems. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-11soc/intel/alderlake: Hook up P2SB PCI opsMichał Żygowski
P2SB device is being hidden from coreboot by FSP-S. This breaks the resource allocator which does not report P2SB BAR via intel common block P2SB driver. Hook up the common block P2SB driver ops to soc_enable function so that the resources will be reported. The P2SB device must be set as hidden in the devicetree. This fixes the silent resource allocation conflicts on machines with devices having big BARs which accidentally overlapped P2SB BAR. TEST=Boot MSI PRO Z690-A with multiple PCIe devices/dGPUs with big BARs and see resource conflicts no longer occur. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I7c59441268676a8aab075abbc036e651b9426057 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-11soc/intel/xeon_sp/acpi: Fix _OSC methodPatrick Rudolph
Fix a couple of bugs in the _OSC method for handling "PCI Host Bridge Device" on Xeon-SP. - Drop the Sleep. The code doesn't write to hardware at all, so there's no need to sleep here. - Make sure that the number of DWORD passed in Arg2 is at least 3. The existing check was useless as it would not create the DWordField, but then use it anyways. - Add check for CXL 2 device method calls which provide a 5 DWORD long buffer to prevent buffer overflows when invoking the "PCI Host Bridge Device" method. Test: Boot on Archer City and confirm that no ACPI errors are reported for _OSC. Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-04-11soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-SMichał Żygowski
According to ADL PCH BIOS specification (DOC# 630603) ADL-S PCH uses a fixed SBREG_BAR of 256MiB starting at 0xe0000000. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69948 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11drivers/fsp2_0/mp_service_ppi: Use struct device to fill in bufferArthur Heymans
Now the CPU topology is filled in struct device during mp_init. Change-Id: I7322b43f5b95dda5fbe81e7427f5269c9d6f8755 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69223 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11soc/intel/{adl, cmn}: Send CSE EOP Async CMD earlySubrata Banik
This patch sends the CSE EOP command asynchronous implementation early as part of `soc_init_pre_device`. Without this patch the duration between asynchronous CSE EOP send and receive commands is not ample whichcauses idle delay while waiting for EOP response. The goal of the CSE async implementation is to avoid idle delay while capturing the response from CSE EOP cmd. This patch helps to create ample duration between CSE EOP command being sent and response being captured. TEST=Able to boot google/marasov EVT sku to ChromeOS and observed ~30ms of boot time savings (across warm and cold reset scenarios). Without this patch: 963:returning from FspMultiPhaseSiInit 907,326 (97,293) ... ... 115:finished elog init 967,343 (2,581) 942:before sending EOP to ME              967,821 (478) …  16:finished LZMA decompress (ignore for x86)    1,017,937 (12,135) 943:after sending EOP to ME                     1,067,799 (49,861) … … 1101:jumping to kernel                          1,144,587 (13,734) Total Time: 1,144,549 With this patch: 963:returning from FspMultiPhaseSiInit 918,291 (97,320) 942:before sending EOP to ME                    918,522 (230)   ... ... 16:finished LZMA decompress (ignore for x86) 1,029,476 (12,483)   943:after sending EOP to ME                     1,033,456 (3,980)   ... ...   1101:jumping to kernel                          1,111,410 (14,007) Total Time: 1,111,375 Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-07soc/intel/common: Order the different types of cores based on APIC IDsSridhar Siricilla
Currently coreboot presents the BSP core first, then efficient cores and Performance cores as indicated below: ``` /sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4 /sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5 /sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6 /sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7 /sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3 /sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3 ``` Existing code presents mix of different cores to OS and causes CPU load balancing and power/performance impact. So, the patch fixes this disorder by ordering the Performance cores first, compute die efficient cores next, and finally SOC efficient cores if they are present. This is done to run the media applications in a power efficient manner, please refer the ChromeOS patches for details: https://chromium-review.googlesource.com/c/chromiumos/platform2/+/3963893 BUG=b:262886449 TEST=Verified the code on Rex system After the fix: ``` /sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1 /sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3 /sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3 /sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4 /sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5 /sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6 /sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7 ``` Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-04-07mb/google/brya: Enable asynchronous End-Of-PostJeremy Compostella
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74215 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-07soc/intel/cmn/cse: Handle EOP completion asynchronouslyJeremy Compostella
coreboot supports three instances of sending EOP: 1. At CSE `.final' device operation 2. Early as with Alder Lake in chip_operations.init if `SOC_INTEL_CSE_SEND_EOP_EARLY' is selected 3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if `SOC_INTEL_CSE_SEND_EOP_LATE' is selected Currently, Alder Lake uses #3 as it results in better and more stable boot time. However, what would deliver even better result is to not actively wait for CSE completion. This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig which split the action of sending EOP request and receiving EOP completion response from the CSE. This patch used in conjunction with #1 can significantly improves the overall boot time on a Raptor Lake design. For example `SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 1 | 1020.052 | 971.272 | | 2 | 1015.911 | 971.821 | | 3 | 1038.415 | 1021.841 | | 4 | 1020.657 | 993.751 | | 5 | 1065.128 | 1020.951 | | 6 | 1037.859 | 1023.326 | | 7 | 1042.010 | 984.412 | |----------+----------+-----------| | Mean | 1034.29 | 998.20 | | Variance | 4.76 % | 5.21 % | The improvement is not stable but comparing coreboot and FSP performance timestamps demonstrate that the slowness is caused by a lower memory frequency (SaGv point) at early boot which is not an issue addressed by this patch. We also observe some improvement on an Alder Lake design. For example, the same configuration on a kano board can deliver up to 10 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 0 | 1067.719 | 1050.106 | | 1 | 1058.263 | 1056.836 | | 2 | 1064.091 | 1056.709 | | 3 | 1068.614 | 1055.042 | | 4 | 1065.749 | 1056.732 | | 5 | 1069.838 | 1057.846 | | 6 | 1066.897 | 1053.548 | | 7 | 1060.850 | 1051.911 | |----------+----------+-----------| | Mean | 1065.25 | 1054.84 | The improvement is more limited on kano because a longer PCIe initialization delays EOP in the Late EOP configuration which make it faster to complete. CSME team confirms that: 1. End-Of-Post is a blocking command in the sense that BIOS is requested to wait for the command completion before loading the OS or second stage bootloader. 2. The BIOS is not required to actively wait for completion of the command and can perform other operations in the meantime as long as they do not involve HECI commands. On Raptor Lake, coreboot does not send any HECI command after End-Of-Post. FSP-s code review did not reveal any HECI command being sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or `END_OF_FIRMWARE' notifications. If any HECI send and receive command has been sent the extra code added in `cse_receive_eop()' should catch it. According to commit 387ec919d9f7 ("soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first boot after flashing of a Marasov board for instance) request coreboot to perform a global request out of AFTER_PCI_ENUM notification. Global request relies on a HECI command. Even though, we tested that it does not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent potential a global reset command to "conflict" with the EOP command. This patch also introduces a new code logic to detect if CSE is in the right state to handle the EOP command. Otherwise, it uses the prescribed method to make the CSE function disable. The typical scenario is the ChromeOS recovery boot where CSE stays in RO partition and therefore EOP command should be avoided. [DEBUG] BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms [INFO ] HECI: coreboot in recovery mode; found CSE in expected SOFT TEMP DISABLE state, skipping EOP [INFO ] Disabling Heci using PMC IPC [WARN ] HECI: CSE device 16.0 is hidden [WARN ] HECI: CSE device 16.1 is disabled [WARN ] HECI: CSE device 16.2 is disabled [WARN ] HECI: CSE device 16.3 is disabled [WARN ] HECI: CSE device 16.4 is disabled [WARN ] HECI: CSE device 16.5 is disabled BUG=b:276339544 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post sent soon after FSP-s and EOP message receive at `BS_PAYLOAD_BOOT'. Verify robustness by injecting a `GET_BOOT_STATE' HECI command with or without `heci_reset'. The implementation always successfully completed the EOP before moving to the payload. As expected, the boot time benefit of the asynchronous solution was under some injection scenario undermined by this unexpected HECI command. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I01a56bfe3f6c37ffb5e51a527d9fe74785441c5a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74214 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-06soc/intel/meteorlake: Perform feature control lockSubrata Banik
This function calls into `set_feature_ctrl_lock()` to lock IA32_FEATURE_CONTROL MSRfeature control. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie9a03ee6786144dae6fd3a18bcc53cb62919dd42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06soc/intel/meteorlake: Enable VMX using coreboot CPU feature programSubrata Banik
This function calls into `set_feature_ctrl_vmx_arg()` to enable VMX for virtualization if not done by FSP (based on DROP_CPU_FEATURE_PROGRAM_IN_FSP config is enabled) in MeteorLake SoC based platform. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06soc/intel/meteorlake: Set AES-NI LockSubrata Banik
This function performs locking of the AES-NI enablement state. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06soc/intel/meteorlake: Disable 3-strike errorSubrata Banik
This patch calls into API to disable 3-strike error on Meteor Lake SoC based platform. TEST=Able to build and boot google/rex to ChromeOS. Dumping MSR 0x1A4 shows BIT11 aka 3-strike error is disabled ``` localhost ~ # iotools rdmsr 0 0x1a4 0x0000000000000900 ``` Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-06soc/intel/meteorlake: Allow to drop redundant CPU feature programmingSubrata Banik
This patch introduces a new config named `DROP_CPU_FEATURE_PROGRAM_IN_FSP` to avoid FSP running basic CPU feature programming on BSP and on APs using the "CpuFeaturesPei.efi" module. Most of this feature programming is getting performed today in scope of coreboot doing MP Init. Running this redundant programming in scope of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled) results in CPU exception (for example: attempting to reprogram CPU feature lock MSR is causing CPU exception). SoC users should select this config after dropping "CpuFeaturesPei.ffs" module from FSP-S Firmware Volume (FV). Upon selection, coreboot runs those additional feature programming on BSP and APs. This feature is by default enabled, in case of "coreboot running MP init" aka `MP_SERVICES_PPI_V2_NOOP` config is selected. At present, this option does not do anything unless any platform eventually decides to drop FSP feature programming module and choose coreboot CPU feature programming over it. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-06soc/intel/cmn/cpu: Add function to disable 3-strike CATERRSubrata Banik
In Intel designs, internal processor errors, such as a processor instruction retirement watchdog timeout (also known as a 3-strike timeout) will cause a CATERR assertion and can only be recovered from by a system reset. This patch prevents the Three Strike Counter from incrementing (as per Intel EDS doc: 630094), which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74158 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-06soc/intel/xeon_sp/spr: Drop devicetree setting X2apicPatrick Rudolph
Drop devicetree setting X2apic as the same functionality is already exposed in Kconfig. To activate X2apic select X2APIC_ONLY or X2APIC_RUNTIME in the "APIC operation mode". Note: Your OS must have support for X2APIC. If you are using less than 256 CPU cores select XAPIC_ONLY here. Test: - Booted to OS in X2APIC mode when X2APIC_ONLY or X2APIC_RUNTIME was selected. - Booted to OS in XAPIC mode when XAPIC_ONLY was selected. Change-Id: I65152b0696a45b62a5629fd95801187354c7a93b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-06soc/intel/xeon_sp/spr: Default to X2APIC supportPatrick Rudolph
When more than 255 CPU cores are present on a board the X2APIC must be used. Select DEFAULT_X2APIC_RUNTIME to support X2APIC by default when a mainboard enables it in the devicetree. Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74184 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-05soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systemsPatrick Rudolph
Inject ACPI code for all generated ASL templates. This fixes ACPI errors shown in linux when not all sockets are currently plugged in or some have been disabled. Test: Boot Archer City with CONFIG_MAX_SOCKET=4 Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74183 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
2023-04-05soc/intel/common/block/pcie/rtd3: Add root port mutex supportCliff Huang
When 'use_rp_mutex' (default = 0) is set in the device tree, a root port mutex will be added. This mutex is used in _ON and _OFF method, where the GPIO reset and/or enable GPIO value is changed. The companion driver, such as WWAN driver, needs to acquire this root port mutex when accessing the same GPIO pins. Using this common mutex prevents those invoked methods from being called from different thread while one is not completed. An example is that WWAN driver calling _RST method to reset the device and does remove/rescan for the device while the pm runtime work might call RTD3 _OFF. For those root port without additional driver, this mutex is not needed. BRANCH=firmware-brya-14505.B TEST=boot to OS and check the generated SSDT table for the root port. The RPMX mutex should be generated and _ON and _OFF should use this mutex. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ibc077528692b2d7076132384fb7bd441be502511 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-04-05Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"Nick Vaccaro
This reverts commit e7a1204f26fe3628de99b4ab4e3f32916565b95c. This initial change was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74207 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-05Revert "mb/google/brya: Enable asynchronous End-Of-Post"Nick Vaccaro
This reverts commit 11f2f88a277124713f7b0023f078fcc2e1a98c32. Revert initial change as it was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74206 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp tableBora Guvendik
Get boot performance timestamps from CSE and inject them into CBMEM timestamp table. 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Able to see TS elapse prior to IA reset on Rex Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73713 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-04soc/intel/alderlake: Add support for CSE timestamp data versionsBora Guvendik
CSE performance data timestamps are different for version 1 Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch moves the current ADL/RPL timestamp definitions to a separate header file. It marks current structure as version 1. BUG=b:259366109 TEST=Boot to OS, check ADL/RPL pre-cpu timestamps. Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-03soc/intel/alderlake: Fix RPL-U 15W and RPL-P 28W TDC current valuesJeremy Compostella
The Intel Power and Performance (PnP) team requested to update the following: - TDC settings for RPL-U 15W variant should be 22A. - TDC settings for RPL-P 28W variant should be 33A. BUG=b:275694022 BRANCH=firmware-brya-14505.B TEST=PnP validated performance impact with these settings on both RPL-U 15W and RPL-P 28W Change-Id: I1141414785a990b975e32ebc03e490b83082aab7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74046 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02soc/intel/common: Order the CPUs based on their APIC IDsSridhar Siricilla
The patch defines acpi_set_cpu_apicid_order() which orders the APIC IDs based on APIC IDs of Performance cores and Efficient cores, calculates the total core count and total Performance cores count, populates the information in the cpu_apicid_order_info struct. The helper function useful to present the Performance and Efficient cores in order to OS through MADT table and _CPC object. TEST=Verify the build for Gimble (Alder Lake board) Change-Id: I8ab6053ffd036185d74d5469fbdf36d48e0021ce Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72131 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02soc/intel/meteorlake: Set Power Performance Platform OverrideSubrata Banik
According to document 640858 MTL EDS Vol2, bit 18 (PWR_PERF_PLATFRM_OVR) of MSR_POWER_CTL must be set. This patch is backported from `commit 117770d32468e63df ("soc/intel/ alderlake: Enable Energy/Performance Bias control")`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic83225b619c49db0b49b521a83a2f1dc1ad69be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74155 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02soc/intel/meteorlake: Add EPP override supportSubrata Banik
This updates energy performance preference value to all logical CPUs when the corresponding chip config is true. This patch is backported from `commit 0bb2225718ef898c ("soc/intel/alderlake: Add EPP override support")`. BUG=b:266522659 TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8172276159fe3987dae36ec30ebceb76dd0ef326 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74154 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02soc/intel/alderlake: Add ADL-P 4+4 with 28W TDPPatrick Rudolph
Add the 28W TDP version of the ADL-P with MCHID 0x4629. Verified that all 28W SoCs have the same PL1/PL2 defined in Intel document #655258 "12th Generation Intel Core Processors Datasheet, Volume 1 of 2". Fixes the error seen in coreboot log: [ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-01soc/intel/xeon_sp/spr: Add ACPI support for Sapphire RapidsJonathan Zhang
Add ACPI support for Sapphire Rapids. Passes FWTS ACPI tests. The code was written from scratch because there are Xeon-SP specific implementation especially Integrated Input/Output (IIO). Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71967 Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-01soc/intel/meteorlake: Add BUILDING_WITH_DEBUG_FSPSubrata Banik
Intel FSP has "debug" build which is not public, used for debugging by approved developers. Add a Kconfig to indicate that coreboot is building with debug version of FSP so we can adjust few things (i.e. flash layout) in the case. BUG=b:262868089 TEST=Able to build and boot google/rex. Change-Id: I5555a2ab4182ad0036c42be6fea3d934ffd0db8c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-01soc/intel/meteorlake: Fix PortUsb30Enable configurationIvy Jian
PortUsb30Enable has been overridden unexpectedly, this patch fixed it. BUG=b:276181378 Test=boot to rex and check USB3 ports are working. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: Ic04b9eb236ed28a76ee516c52fc0c983cb8f2c0e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-01soc/intel/meteorlake: Enable 'struct cpu_info' update for MTLSridhar Siricilla
The patch enables addition of core_type member to 'struct cpu_info' for MeteorLake platform. TEST=Build and verify the code for Rex Change-Id: I01abed6b87bec2f8eb39bfc941faff070b83abe6 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74130 Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-31mb/google/brya: Enable asynchronous End-Of-PostJeremy Compostella
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-31soc/intel/cmn/cse: Handle EOP completion asynchronouslyJeremy Compostella
coreboot supports three instances of sending EOP: 1. At CSE `.final' device operation 2. Early as with Alder Lake in chip_operations.init if `SOC_INTEL_CSE_SEND_EOP_EARLY' is selected 3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if `SOC_INTEL_CSE_SEND_EOP_LATE' is selected Currently, Alder Lake uses #3 as it results in better and more stable boot time. However, what would deliver even better result is to not actively wait for CSE completion. This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig which split the action of sending EOP request and receiving EOP completion response from the CSE. This patch used in conjunction with #1 can significantly improves the overall boot time on a Raptor Lake design. For example `SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 1 | 1020.052 | 971.272 | | 2 | 1015.911 | 971.821 | | 3 | 1038.415 | 1021.841 | | 4 | 1020.657 | 993.751 | | 5 | 1065.128 | 1020.951 | | 6 | 1037.859 | 1023.326 | | 7 | 1042.010 | 984.412 | |----------+----------+-----------| | Mean | 1034.29 | 998.20 | | Variance | 4.76 % | 5.21 % | The improvement is not stable but comparing coreboot and FSP performance timestamps demonstrate that the slowness is caused by a lower memory frequency (SaGv point) at early boot which is not an issue addressed by this patch. We also observe some improvement on an Alder Lake design. For example, the same configuration on a kano board can deliver up to 10 ms boot time improvement as illustrated below. | # | Late EOP | Async EOP | |----------+----------+-----------| | 0 | 1067.719 | 1050.106 | | 1 | 1058.263 | 1056.836 | | 2 | 1064.091 | 1056.709 | | 3 | 1068.614 | 1055.042 | | 4 | 1065.749 | 1056.732 | | 5 | 1069.838 | 1057.846 | | 6 | 1066.897 | 1053.548 | | 7 | 1060.850 | 1051.911 | |----------+----------+-----------| | Mean | 1065.25 | 1054.84 | The improvement is more limited on kano because a longer PCIe initialization delays EOP in the Late EOP configuration which make it faster to complete. CSME team confirms that: 1. End-Of-Post is a blocking command in the sense that BIOS is requested to wait for the command completion before loading the OS or second stage bootloader. 2. The BIOS is not required to actively wait for completion of the command and can perform other operations in the meantime as long as they do not involve HECI commands. On Raptor Lake, coreboot does not send any HECI command after End-Of-Post. FSP-s code review did not reveal any HECI command being sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or `END_OF_FIRMWARE' notifications. If any HECI send and receive command has been sent the extra code added in `cse_receive_eop()' should catch it. According to commit 387ec919d9f7 ("soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first boot after flashing of a Marasov board for instance) request coreboot to perform a global request out of AFTER_PCI_ENUM notification. Global request relies on a HECI command. Even though, we tested that it does not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent potential a global reset command to "conflict" with the EOP command. BUG=b:276339544 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post sent soon after FSP-s and EOP message receive at `BS_PAYLOAD_BOOT'. Verify robustness by injecting a `GET_BOOT_STATE' HECI command with or without `heci_reset'. The implementation always successfully completed the EOP before moving to the payload. As expected, the boot time benefit of the asynchronous solution was under some injection scenario undermined by this unexpected HECI command. Change-Id: Ib09dcf9140eb8a00807a09e2af711021df4b416f Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73619 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-31soc/intel/alderlake: Enable 'struct cpu_info' update for ADLSridhar Siricilla
The patch enables addition of core_type member to 'struct cpu_info' for Alderlake platform. TEST=Build and verify the code for Gimble Change-Id: Ia065b98c2013e78328fd38bed9c667792d6d1f4d Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74089 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-31soc/intel/common: Add core_type member to 'struct apic_path'Sridhar Siricilla
The patch adds new member 'core_type' to the 'struct apic_path' and updates core type information. TEST=Build the code for MTL Change-Id: I1d34068fd5ef43f8408301bf3effa9febf85f683 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74088 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-30soc/intel/alderlake: Avoid reprogramming the SRAM BARSubrata Banik
This patch avoids the redundant programming of SRAM BAR when the SRAM PCI device is enabled. Rather read the PCH SRAM Base Address Register while enabling crashlog feature. Additionally, this patch relies on PCI enumeration to get the SRAM BAR rather than hijacking the SPI temporary base address which might have resulted in problems if SPI is disabled on some platform with BAR being implemented. TEST=Able to build and boot google/marasov and crashlog is working. Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-29soc/intel/common: Add Intel Trace Hub driverPratikkumar Prajapati
From Meteor Lake onwards Intel FSP will generate the Trace Hub related HOB if the Trace Hub is configured to save data in DRAM. This memory region is used by Trace Hub to store the traces for debugging purpose. This driver locates the HOB and marks the memory region reserved so that OS does not use it. Intel Trace Hub developer manual can be found via document #671536 on Intel's website. Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-03-29soc/intel/cmn/crashlog: Add check for zero based SRAM BARSubrata Banik
This patch adds a check for zero based SRAM base address. It will help to avoid running into problems if the SRAM is disabled and the base address register is zero. TEST=Able to build and boot google/marasov with PCH SRAM being disabled. Change-Id: Iebc9dc0d0851d5f83115f966bf3c7aad1eb6bc01 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-28soc/intel/xeon_sp: Use simple device function for setting PMAX_LOCKJonathan Zhang
Change to use simple device function for setting PMAX_LOCK because the Sapphire Rapids PCU device is not scanned during coreboot PCIe bus scan and would see "PCI: dev is NULL!" failure. Change-Id: I3156a6adf874b324b5f4ff5857c40002220e47ab Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72400 Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-26soc/intel: Move USB PORTSC definition into IA common codeSubrata Banik
This patch moves USB Port Status and Control (PORTSC) Reg definition into IA common code to allow other SoC code to reuse it without redefining the same for each SoC. TEST=Able to build and boot google/taeko where USB wake is working. Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-25soc/intel/xeon_sp/chip_common.c: Probe all buses in attach_iio_stacks()Jonathan Zhang
For some Xeon-SP (such as SPR-SP), more buses should be probed. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-25soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP supportTim Chu
Add support for Intel SPR-SP to uncore_acpi.c. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com> Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-24soc/intel/xeon_sp/smihandler.c: enable support for spr-spTim Chu
For SPR-SP, the SMM_FEATURE_CONTROL register is in UBOX_URACU_FUNC instead of UBOX_DEV_PMON. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: Ide46c5f9cdf65b7e05552449b08ad4d7246664cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-23soc/intel/xeon_sp: Report platform cpu infoNaresh Solanki
Add platform cpu info for known microcode, print cpuid & processor branding string. This will print as in the following example: CPU: Intel(R) Xeon(R) Platinum 8468H CPU: ID 806f6, Sapphire Rapids E3, ucode: 2b000130 CPU: AES supported, TXT supported, VT supported Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-23soc/intel/xeon_sp: Fix PCH IOAPIC IDPatrick Rudolph
FSP may program a different ID under certain circumstances. Read IOAPIC ID from hardware instead of using some define that might not reflect how hardware is configured. Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-23soc/intel/cmn/cse: Make heci_(send|receive) public functionsJeremy Compostella
Having these two functions public allow "asynchronous" HECI command implementation. Typically, these function can be use to implement an asynchronous End-Of-Post. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Successful compilation for brya0 Change-Id: I7d029bb9af4b53f219018e459d17df9c1bd33fc1 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73710 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-23soc/intel/elkhartlake: Define DIMM_SPD_SIZE in SoC KconfigMichał Żygowski
The default SPD size is set to 256 bytes, instead of 512 for LPDDR4/DDR4 if not overridden by the mainboard Kconfig. This caused the SMBus libraries to read only the lower half of the DIMM SPD on protectli/vault_ehl. The lower half of the SPD passed to FSP causes a bug in DIMM change detection, which relies on the CRC of the manufacturer bytes in the upper half of the SPD (CRC of zero bytes always gives zero so no change was assumed). Setting the DIMM SPD size to 512 fixes it. Setting the SPD size in SoC will also avoid such problems in the future Elkhart Lake ports. Elkhart Lake supports only LPDDR4/DDR4 so providing the correct default of 512 bytes is an obvious thing to do. TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see FSP is retraining the memory instead of doing the fastboot with old DIMM data. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I998ed8781951034419cadc26c04ff1e0a124b267 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73933 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23soc/intel: Rename IA common code module from `TOM` to `RAMTOP`Subrata Banik
This patch renames all references of `top_of_ram` (TOM) in IA common `basecode` module (for example: functions, variables, Kconfig, Makefile and comments) with `ramtop` aka top_of_ram to make it more meaningful and to avoid conflicts with Intel SA chipset TOM registers. BUG=Able to build and boot google/rex with the same ~49ms savings in place. Change-Id: Icfe6300a8e4c5761064537fb256cfecbe2afb2d8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73881 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23intel/common/block/smm: remove return statements from void functionsYuchen He
To be consistent with other occurrences in soc/intel/common, remove the return statements of weak void funtions since they are not generally useful. Found by the linter. Signed-off-by: Yuchen He <yuchenhe126@gmail.com> Change-Id: I3fb8217cfcae65b5dc317458b59aa431f1ccdaef Reviewed-on: https://review.coreboot.org/c/coreboot/+/73866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-22soc/intel/xeon_sp/uncore.c: Add CXL memory into memory mapJonathan Zhang
If the host supports CXL, get proximity domain info from FSP HOB. The proximity domains may include both processor domains and CXL domains. Add header definition for proximity domain. Add CXL memory into memory map. Change-Id: If3f856958a3e6ed3909240ee455bb639e487087f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72617 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/uncore.c: skip configuring VTD devJonathan Zhang
DPR should not be configured for VTD devices of other stacks for SPR-SP. Such processor(s) would be configured with SOC_INTEL_MMAPVTD_ONLY_FOR_DPR. Change-Id: Ib33b1b62f59a10d362c6585b1403490d4a1aedeb Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72616 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/uncore.c: Add NCMEM base/limit to map entriesJonathan Zhang
... instead of ME base/limit if the processor is configured with SOC_INTEL_HAS_NCMEM. Change-Id: I95783cad1a2d5a3599d120ea0c98e2aa8703bdb4 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72615 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp/spr: Add soc set_cmos_mrc_cold_boot_flagJohnny Lin
This soc utility function can set cmos flag to enforce FSP MRC training. Change-Id: I88004cbfdcbe8870726493576dfc31de4b6036a9 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/xeon_sp: Enable FSP_ERROR_INFO_HOB handlingTim Chu
After calling FSP MemoryInit API, if there is an error, some FSPs (such as SPR-SP FSP) is capable of generating FSP_ERROR_INFO_HOB. Check existence of such a HOB and handle it accordingly. Change-Id: Icb5c31daa223ba6b06ba1b2de4f8808e0b27899e Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22soc/intel/elkhartlake: Increase BSP stack size by 1 KiB to 193 KiBMichał Żygowski
The Kconfig help section says FSP uses 192 KiB of stack (0x30000) and coreboot's romstage requires ~1 KiB, but it is not satisfied currently. Increase the BSP stack size by the missing 1KiB for romstage like other SoCs do. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iddd4a4613bc174aec4331732371a27450225258c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73820 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-21soc/intel/xeon_sp/spr/cpu: add missing device_match_mask in CPU tableFelix Held
Commit 6a6ac1e0b929 ("arch/x86/cpu: introduce and use device_match_mask") added the device_match_mask element to the cpu_device_id struct and uses it to be able to mask off for example the stepping ID when checking for CPU table entry that matches the silicon the code is running on. Commit 3ed903fda9cb ("soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage code") added a CPU table that was missing the device_match_mask which results in this being 0, so the first entry of the CPU table would match for any Intel CPU which isn't the intended behavior. Also use CPU_TABLE_END instead of the final {0, 0, 0} array element. Likely all entries could be replaced by one entry that uses the CPUID_ALL_STEPPINGS_MASK instead of the CPUID_EXACT_MATCH_MASK, but that's out of scope for this fix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib0be2e9fe3c31487c83c9b1cf305a985416760b5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73835 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-21soc/intel/apl: Fix programming temporary MTRR on GLKArthur Heymans
Programming MTRR happens later in the CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT codepath. fast_spi_cache_bios_region() assumes an existing MTRR solution from x86_setup_mtrrs_with_detect(). This fixes a problem introduced by 829e8e6 "soc/intel: Use common codeflow for MP init". Change-Id: I9b6130cf76317440ebe7a7a53e460e2b658d198e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73836 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-21soc/intel/common/block/acpi: Support more than 255 coresPatrick Rudolph
Replace the legacy ACPI Processor() object as it only supports 8bit IDs and thus no more than 255 cores. Use the new ACPI Device() object that supports more than 255 cores. Test: - Observed no ACPI errors on IBM/SBP1 and Linux 5.15 running 384 CPU cores in total. - Verified on Intel ADL RVP with 20 cores that Linux 5.15 is still working without errors. Change-Id: I309c06b6824704c84fd16534655334a6f269904a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73578 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-03-21soc/intel/elkhartlake: Make PCIe root port speed limit configurableMario Scheithauer
In cases where there are limitations on the connected device behind the PCIe root port it can be necessary to limit the speed. The FSP parameter 'PcieRpPcieSpeed' allows to set the speed limit. This patch provides a chip config so that this FSP parameter can be set as needed in the devicetree on mainboard level. Change-Id: I9fc24de1682279e4ae4c090147a6ef7995b441bc Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73766 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-21soc/intel/alderlake/vr_config: Add i3-1220PEPatrick Rudolph
Add the AlderLake-P 4+4+2 (28W) with MCH_ID 0x4629 to the vr_config table. Change-Id: I606ef429f47dfe386177f7257b153acc1611bb61 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-20soc/intel/meteorlake: Enable GPIO IOSTANDBY configurationSubrata Banik
Enable SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY so the pads can be configured with non-zero IOSSTATE values. TEST=Able to build and boot google/rex. GPIO debug print is showing GPIO PAD config DW1 bit[14:17] are getting programmed. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9e63fe946d541769fa0ddbb23f902f9c905735c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73757 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-19soc/intel/xeon_sp/Makefile.inc: Build EBG for SPR-SPTim Chu
Intel SPR-SP chipset has EBG instead of LBG. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I9429fe332bb5f01a41aa205c76ad9f0159f93eee Reviewed-on: https://review.coreboot.org/c/coreboot/+/71959 Reviewed-by: Jian-Ming Wang <jianmingW@supermicro.com> Reviewed-by: TimLiu-SMCI <timliu@supermicro.com.tw> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp/spr: Add Sapphire Rapids ramstage codeJonathan Zhang
It implements SPR ramstage including silicon initialization, MSR programming, MP init and certain registers locking before booting to payload. Change-Id: I128fdc6e58c49fb5abf911d6ffa91e7411f6d1e2 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/xeon_sp/spr: Add header files and romstage codeJonathan Zhang
Several FSP HOBs processing codes are similar to Intel Cooperlake-SP codes in soc/intel/xeon_sp/cpx. Register datasheet please reference Sapphire Rapids EDS Vol2 Doc#612246 and Emmitsburg PCH EDS Doc#606161. Change-Id: Ia022534e5206dbeec946d3e5f3c66bcb5628748f Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-19soc/intel/mtl: Choose serial msg `log_level` based on DIMM countSubrata Banik
This patch modifies the serial msg log_level at runtime to highlight an ERROR if the DIMM count is zero. It would help to draw the attention while parsing the serial msg and catch any underlying issue. TEST=Able to see ERROR msg while booting google/rex with FSP v3064 Without this patch: [DEBUG] 0 DIMMs found With this patch:     [ERROR]  No DIMMs found Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iacf41efecb4962f91cf322bbc50636dc44033e3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73756 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-19soc/intel/xeon_sp: add MSR definitions for SPR-SPDavid Hendricks
Some MSRs used in SPR code are common among currently supported Xeon-SP generations and are added to the top-level Xeon-SP msr.h. MSRs which have changed are added to SPR's soc_msr.h. Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I92b433a9686734716dc7936895fb79c7751f7f9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Split SKX/CPX MSRs into separate headersJonathan Zhang
Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: David Hendricks <ddaveh@amazon.com> Change-Id: I2ecfebdde453a48b7b0e6f21b3c4394411eed671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-19soc/intel/xeon_sp: Add P2SB definition for SPR-SPJonathan Zhang
Change-Id: I2ece7aac4339266068d4fc8fb1c58d0573eb2895 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Chou <simonchou@supermicro.com.tw> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2023-03-17soc/intel/alderlake: Hook the VT-d DMA protection optionMichał Żygowski
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iecaa3d04f1447b7e73507ca57a0d23d42e24d663 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68450 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake/hsphy.c: Handle case with DMA protectionMichał Żygowski
The HSPHY firmware must be downloaded to DMA-allowed host address space. Check for DMA buffer presence and use it as the buffer for HSPHY firmware to be downloaded from CSME. TEST=Successfully load HSPHY firmware to CPU on MSI PRO Z690-A DDR4 with DMA protection enabled. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68556 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_VTDMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I226305fa547e9d9ea541a5806d543aa358bce28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72069 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17intelblocks/vtd: Add VT-d block with DMA protection APIMichał Żygowski
Add new common block with VT-d/IOMMU support. The patch adds an option to enable DMA protection with PMR. However the payload and OS must support VT-d in order to properly handle I/O devices. TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Id7edf982457c1139624e5cd383788eda41d6a948 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-03-15soc/intel/xeon_sp: Rename nb_acpi.c to uncore_acpi.cJohnny Lin
With newer xeon_sp processors, the concept of "north bridge" became obsolete, instead uncore should be used. Therefore we use uncore_acpi.c (instead of nb_acpi.c) going forward. Change-Id: I91ec9023152996bf9f2300a369aff3c4f19d75fd Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-15soc/intel/tigerlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I97c8c07db9b44aa89b433e7962ec77c8501ecaa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-15soc/intel/elkhartlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8f8a0bfeaea508d3b4ad1b3fe2e68742cbab5570 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73687 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/intel/coffeelake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: Icd3d16ab2cb34dc81fc12ec139c52ecaa170528d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73686 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/intel/alderlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I1fe6072a3c23a02c9a691406f179bfc8f0f18a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
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