coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-01-01	soc/intel/tigerlake/fsp_params.c: Use `is_dev_enabled()`	Felix Singer
2021-12-09	soc/intel/tigerlake: Hook up DPTF device to devicetree	Felix Singer
2021-10-18	intel/tigerlake: Add missing IRQ for CNVi	Sean Rhodes
2021-10-17	soc/intel: transition full control over PM Timer from FSP to coreboot	Michael Niewöhner
2021-09-16	drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling method	Subrata Banik
2021-09-10	soc/intel/tigerlake: Move LPM functions to new file	Tim Wawrzynczak
2021-08-26	soc/intel/tigerlake: Lock PAM registers in finalize	Tim Wawrzynczak
2021-08-24	soc/intel/tigerlake: Add PCH-H GPIO definitions	Jeremy Soller
2021-08-12	soc/intel/tigerlake: Clean up FSP chipset lockdown configuration	Felix Singer
2021-08-12	soc/intel/tgl: Allow setting PCIe subsystem IDs after FSP-S	Tim Crawford
2021-08-03	soc/intel/*: Allow configuring 8254 timer via CMOS	Sean Rhodes
2021-07-17	soc/intel/tigerlake: Make use of `cpu/intel/cpu_ids.h'	Subrata Banik
2021-07-01	soc/intel: Refactor `xdci_can_enable()` function	Angel Pons
2021-06-30	soc/intel/tigerlake: Send End-of-Post message to CSE	Tim Wawrzynczak
2021-06-29	soc/intel/tigerlake: Enable support for common IRQ block	Tim Wawrzynczak
2021-06-23	soc/intel/tigerlake: Use devfn_disable() function for XDCI	Subrata Banik
2021-06-16	soc/intel/tigerlake: Make use of is_devfn_enabled() function	Subrata Banik
2021-06-10	soc/intel/tigerlake: Hook up FSP repository	Felix Singer
2021-06-07	soc/intel: Drop unused lpss functions	Furquan Shaikh
2021-05-14	soc/intel/tigerlake: Allow devicetree to fill UPD related to TCSS OC	Nick Vaccaro
2021-05-06	soc/intel/tgl,mb/google/volteer: Add API for Type-C aux bias pads	Tim Wawrzynczak
2021-04-06	intel/tigerlake: Add Acoustic features	Shaunak Saha
2021-03-28	soc/intel/tigerlake: Move TCSS code to intel/common/block	Tim Wawrzynczak
2021-03-19	soc/intel/tgl: Add configurable value for PmcUsb2PhySusPgEnable	Derek Huang
2021-03-15	soc/intel/tigerlake: Add CNVi Bluetooth flag at devicetree entry	Cliff Huang
2021-03-05	soc/intel/tigerlake: Enable TCSS Muxes to disconnect mode during boot	Brandon Breitenstein
2021-03-05	soc/tigerlake: Fix TCSS code to calling back and forth to mainboard and soc	Brandon Breitenstein
2021-02-22	soc/intel/tigerlake: Enable end of post support in FSP	Nick Vaccaro
2021-02-10	soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design	Shreesh Chhabbi
2021-01-14	soc/intel/tgl: Add configurable value for UsbTcPortEn	Brandon Breitenstein
2021-01-13	soc/intel/tigerlake: Disable TC cold support	Srinidhi N Kaushik
2021-01-08	soc/intel/tigerlake: Enable USB2 port reset message on Type-C ports	John Zhao
2020-11-20	soc/intel/tigerlake: Expose UPD to enable Precision Time Measurement	Duncan Laurie
2020-11-13	soc/intel/tigerlake: Add code for early tcss	Brandon Breitenstein
2020-11-05	soc/intel/tigerlake: Disable C1 C-state Demotion	Ravi Sarawadi
2020-10-23	soc/intel/tigerlake: Add Acoustic features	Shaunak Saha
2020-09-24	soc/intel/tigerlake: Add support for CnviBtCore and CnviBtAudioOffload	John Zhao
2020-09-23	soc/intel/tigerlake: Configure FSP UPDs for minimum assertion widths	Jamie Ryu
2020-09-06	soc/intel: skl,cnl,icl,jsl,tgl: disable usb over-current pin by default	Michael Niewöhner
2020-09-02	soc/intel/tigerlake: Add mainboard hook for overriding SoC config	Jes Klinke
2020-08-17	soc/intel/tigerlake: Allow fine grained control of S0iX states	Jes Klinke
2020-08-01	soc/intel/{icl,jsl,tgl}: Remove SkipMpInit UPD as deprecated	Subrata Banik
2020-07-29	soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold	John Zhao
2020-07-28	soc/intel/tigerlake: Simplify is-device-enabled checks	Felix Singer
2020-07-26	src: Update bare access to BOOL CONFIG_ vals to CONFIG()	Martin Roth
2020-07-21	soc/intel/tigerlake: Select PLATFORM_USES_FSP2_2	Subrata Banik
2020-07-15	soc/intel/tigerlake: Hook up SATA Port Enable DITO UPDs	Shaunak Saha
2020-07-03	soc/intel/tigerlake: Disable hybrid storage mode in CSE Lite RO boot	Jamie Ryu
2020-06-30	tigerlake: enable tcc_offset functionality	Sumeet R Pawnikar
2020-06-17	soc/soch/intel/tigerlake: Integrate PCIe hot-plug config UPD	Wonkyu Kim
2020-06-12	soc/intel/tigerlake: Add devicetree support to change PCH VR settings	Venkata Krishna Nimmagadda
2020-06-09	soc/intel/tigerlake: Set FSPS UPD ITbtConnectTopologyTimeoutInMs	John Zhao
2020-05-28	soc/intel/tigerlake: Configure THC	Wonkyu Kim
2020-05-26	soc/intel/tigerlake: Disable VMD	Wonkyu Kim
2020-05-26	soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnable	John Zhao
2020-05-20	tigerlake: enable DPTF functionality for volteer	Sumeet R Pawnikar
2020-05-20	soc/tigerlake: Add devicetree configurability for IomTypeCPortPadCfg	Brandon Breitenstein
2020-05-12	soc/intel/tigerlake: Control SATA and DMI power optimization	Shaunak Saha
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
2020-05-01	soc/intel/tigerlake: Fill PcieRpClkReqDetect from devicetree	Meera Ravindranath
2020-04-20	soc/intel/tigerlake: Merge the recent change from other platforms	Wonkyu Kim
2020-04-14	soc/intel/tigerlake: Implement CHIPSET_LOCKDOWN	Wonkyu Kim
2020-04-14	soc/intel/tigerlake: Configure RP setting	Wonkyu Kim
2020-04-06	soc/intel/tigerlake: Use SPDX for GPL-2.0-only files	Angel Pons
2020-04-01	soc/intel/tigerlake: Remove Jasper Lake SoC references	Aamir Bohra
2020-01-13	soc/intel/tigerlake: Select correct fsp_param as per SoC Kconfig	Maulik V Vaghela
2019-12-11	soc/intel/tigerlake: Include soc common lpss header file	Aamir Bohra
2019-11-09	soc/intel/tigerlake: Do initial SoC commit till ramstage	Subrata Banik