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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-07-19 16:07:42 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-09-10 21:53:48 +0000
commit90f9cbbfc4ae1f03028176b124c2be54e579fd3f (patch)
tree518b111b21a9ec32dafe3b8b26ed327a29e60098 /src/soc/intel/tigerlake/fsp_params.c
parent5faee2ed0f9d6e2a6a3ccca880eb57d616bea799 (diff)
soc/intel/tigerlake: Move LPM functions to new file
The LPM enable mask is useful to have in more than one place, therefore more the get_disable_mask() function and its helpers to lpm.c Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ibe83dc106f5f37baf9d5c64f68c47d85ea4e6dd4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56460 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/tigerlake/fsp_params.c')
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c50
1 files changed, 2 insertions, 48 deletions
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 15ba280b92..bb100df633 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -22,6 +22,7 @@
#include <security/vboot/vboot_common.h>
#include <soc/gpio.h>
#include <soc/intel/common/vbt.h>
+#include <soc/lpm.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <soc/soc_chip.h>
@@ -69,53 +70,6 @@ static int get_l1_substate_control(enum L1_substates_control ctl)
return ctl - 1;
}
-/* Function returns true if the platform is TGL-UP3 */
-static bool platform_is_up3(void)
-{
- const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
- u32 cpu_id = cpu_get_cpuid();
- uint16_t mchid = pci_read_config16(dev, PCI_DEVICE_ID);
-
- if ((cpu_id != CPUID_TIGERLAKE_A0) && (cpu_id != CPUID_TIGERLAKE_B0))
- return false;
-
- return ((mchid == PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2) ||
- (mchid == PCI_DEVICE_ID_INTEL_TGL_ID_U_4_2));
-}
-
-static int get_disable_mask(struct soc_intel_tigerlake_config *config)
-{
- int disable_mask;
-
- /* Disable any sub-states requested by mainboard */
- disable_mask = config->LpmStateDisableMask;
-
- /* UP3 does not support S0i2.2/S0i3.3/S0i3.4 */
- if (platform_is_up3())
- disable_mask |= LPM_S0i3_3 | LPM_S0i3_4 | LPM_S0i2_2;
-
- /* If external bypass is not used, S0i3 isn't recommended. */
- if (config->external_bypass == false)
- disable_mask |= LPM_S0i3_0 | LPM_S0i3_1 | LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4;
-
- /* If external clock gating is not implemented, S0i3.4 isn't recommended. */
- if (config->external_clk_gated == false)
- disable_mask |= LPM_S0i3_4;
-
- /*
- * If external phy gating is not implemented,
- * S0i3.3/S0i3.4/S0i2.2 are not recommended.
- */
- if (config->external_phy_gated == false)
- disable_mask |= LPM_S0i3_3 | LPM_S0i3_4 | LPM_S0i2_2;
-
- /* If CNVi or ISH is used, S0i3.2/S0i3.3/S0i3.4 cannot be achieved. */
- if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI) || is_devfn_enabled(PCH_DEVFN_ISH))
- disable_mask |= LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4;
-
- return disable_mask;
-}
-
static void parse_devicetree(FSP_S_CONFIG *params)
{
const struct soc_intel_tigerlake_config *config;
@@ -483,7 +437,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
* LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0,
* LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4
*/
- params->PmcLpmS0ixSubStateEnableMask = LPM_S0iX_ALL & ~get_disable_mask(config);
+ params->PmcLpmS0ixSubStateEnableMask = get_supported_lpm_mask(config);
/*
* Power Optimizer for DMI and SATA.