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path: root/src/soc/intel/common/block/cpu
AgeCommit message (Expand)Author
2024-05-14soc/intel/common: Add Panther Lake DIDsSaurabh Mishra
2024-05-12soc/intel/lunarlake: Support stepping A0_2Saurabh Mishra
2024-04-04soc/intel/cache_as_ram_fsp.S: Drop unused preprocessing directivesArthur Heymans
2024-04-04drivers/intel/fsp2_0: Support FSP-T in long modeArthur Heymans
2024-03-30soc/intel: Remove blank lines before '}' and after '{'Elyes Haouas
2024-03-28cpu/x86: Link page tables in stage if possibleArthur Heymans
2024-03-09soc/intel/common/mp_init: Fix USE_INTEL_FSP_MP_INIT use-caseJeremy Compostella
2024-03-05soc/intel: Add definition of D0 stepping for TigerLake HaloAlicja Michalska
2024-02-18soc: Add SPDX license headers to Kconfig filesMartin Roth
2024-02-08cpu/x86/64bit: Turn jumping to long mode into a macroArthur Heymans
2024-01-26soc/intel/common: Add lunarlake device IDsAppukuttan V K
2024-01-24soc/intel: Rename Makefiles from .inc to .mkMartin Roth
2023-12-15soc/intel/cmn/cpu: Introduce API to disable signaling 3-strike eventSubrata Banik
2023-09-14x86: Add .data section support for pre-memory stagesJeremy Compostella
2023-09-12cpu/intel: Move is_tme_supported() from soc/intel to cpu/intelJeremy Compostella
2023-09-01soc/intel/cpu: Only show MP PPI option when meaningfulArthur Heymans
2023-08-05src/*/post_code.h: Change post code prefix to POSTCODEYuchen He
2023-08-03soc/intel/common: Merge TME new key gen and exclusion range configsPratikkumar Prajapati
2023-07-12intelblocks/cpu/mp_init: Add missing ADL-S SKUs to CPU match tableMichał Żygowski
2023-07-12treewide: Drop the suffixes from ADL and RPL CPUID macros and stringsMichał Żygowski
2023-07-12soc/intel/alderlake: Add support for Raptor Lake S CPUsMax Fritz
2023-06-29soc/intel/meteorlake: Add QS(C0) stepping CPU IDMusse Abdullahi
2023-06-23commonlib/console/post_code.h: Change post code prefix to POSTCODElilacious
2023-06-16soc/intel/common: Add configs for TME exclusion range and new key genPratikkumar Prajapati
2023-04-15soc/intel/meteorlake: Add B0 stepping CPU IDMusse Abdullahi
2023-04-11drivers/fsp2_0/mp_service_ppi: Use struct device to fill in bufferArthur Heymans
2023-04-06soc/intel/cmn/cpu: Add function to disable 3-strike CATERRSubrata Banik
2023-02-25soc/intel/{adl, cmn, mtl}: Refactor MP Init related configsSubrata Banik
2023-02-23soc/intel: Use common codeflow for MP initArthur Heymans
2023-02-09arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminatorFelix Held
2023-02-09treewide: Remove repeated wordsElyes Haouas
2023-02-08arch/x86/cpu: introduce and use device_match_maskFelix Held
2023-01-19tree: Drop Intel Ice Lake supportFelix Singer
2023-01-08soc/intel/common: Untie PRMRR from SGXPratikkumar Prajapati
2023-01-06soc/intel/common: Check PRMRR dependent featuresPratikkumar Prajapati
2023-01-06soc/intel/common: Add Kconfig option for Intel Key LockerPratikkumar Prajapati
2023-01-06soc/intel/common: Use CPUID_STRUCT_EXTENDED_FEATURE_FLAGS macroPratikkumar Prajapati
2023-01-04soc/intel/common: Add API to check Key Locker supportPratikkumar Prajapati
2023-01-02soc/intel/common: Move SGX supported API to cpulibPratikkumar Prajapati
2022-12-25soc/intel: Move max speed API to commonDinesh Gehlot
2022-12-16cpu/intel: Fix clearing MTRR for clang 64bitArthur Heymans
2022-11-23soc/intel/common: Define post codesMartin Roth
2022-11-04soc/intel: Include <cpu/cpu.h> instead of <arch/cpu.h>Elyes Haouas
2022-10-31soc: Add SPDX license headers to MakefilesMartin Roth
2022-09-16soc/intel/cnl: Add Cometlake-H/S Q0 (10+2) CPU IDJeremy Soller
2022-09-06src: remove force-included header rules.h from individual filesMartin Roth
2022-08-22soc/intel/cmn/cpu: API to set TME core activationSubrata Banik
2022-08-21soc/intel/common/block/cpu: API to check if TME is supportedSubrata Banik
2022-08-21soc/intel: Unravel `INTEL_TME` Kconfig optionAngel Pons
2022-08-16soc/intel/common/cpu: Remove the address-of (`&`) operator usageSubrata Banik
2022-07-20treewide: Remove unused <cpu/x86/msr.h>Elyes Haouas
2022-07-09*/fsp/exit_car: Push stack address into %espArthur Heymans
2022-06-28soc/intel: Add Raptor Lake device IDszhixingma
2022-06-22soc/intel/mp_init: Skip before_post_cpus_init if !USE_COREBOOT_MP_INITSubrata Banik
2022-06-22soc/intel/cmn/block/cpu: Perform PRMRR sync on all coresSubrata Banik
2022-06-22intel/mp_init: Call `intel_reload_microcode()` before post_cpus_init()Subrata Banik
2022-06-14soc/intel/cmn/cpu: API to initialize core PRMRRSubrata Banik
2022-06-14soc/intel/common: Remove use of CPUID_EXTENDED_CPU_TOPOLOGY_V2Ronak Kanabar
2022-06-09soc/intel/cmn/mp_init: Reload microcode patch before post_cpus_init()Subrata Banik
2022-06-07soc/intel/cmn/mp_init: Create helper function to load microcodeSubrata Banik
2022-06-07soc/intel/cmn/block/cpu: Set BIOS_DONE on all CPUsSubrata Banik
2022-05-26soc/intel/skylake: Move FSP_HYPERTHREADING to common Intel KconfigFelix Singer
2022-05-18intel/common/block: Provide RAPL and min clock ratio switches in commonUwe Poeche
2022-05-16soc/intel: Add Raptor Lake device IDsBora Guvendik
2022-05-16soc/intel/common: Use mp_run_on_all_cpus_synchronously for APs MTRR initKane Chen
2022-05-16soc/intel: Remove unused <cpu/intel/common/common.h>Elyes HAOUAS
2022-04-04soc/intel/alderlake: Add new CPU IDLean Sheng Tan
2022-04-04soc/intel/alderlake: Update CPU IDs with correct steppingsLean Sheng Tan
2022-04-01arch/x86/postcar: Use a separate stack for C executionArthur Heymans
2022-03-17soc/intel/common/block/cpu: Enable ROM caching in ramstageSubrata Banik
2022-03-09soc/intel/common: Include Meteor Lake device IDsWonkyu Kim
2022-01-11soc/intel/apl: Rework on CPU privilege level implementationSubrata Banik
2022-01-10soc/intel/common: Add missing space before }Paul Menzel
2021-12-13soc/intel/common/block/cpu/car/exit_car_fsp.S: Align stackArthur Heymans
2021-12-06soc/intel/common: Refactor cpu_set_p_state_to_max_non_turbo_ratioSridhar Siricilla
2021-12-06soc/intel/common: Add CPU related APIsSridahr Siricilla
2021-11-29soc/intel/common: Include Alder Lake-N device IDsUsha P
2021-11-18drivers/fsp: Rewrite post code hex values in lowercaseSean Rhodes
2021-10-22cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held
2021-10-17soc/intel/*: only enable PM Timer emulation if the PM Timer is disabledMichael Niewöhner
2021-10-05src/soc to src/superio: Fix spelling errorsMartin Roth
2021-10-02soc/intel/common: round PM Timer emulation frequency multiplierMichael Niewöhner
2021-09-30soc/intel/alderlake: Add CPU ID 0x906a4Meera Ravindranath
2021-09-20soc/intel/{common,tgl,adl}: guard TME Kconfig option by SoC supportMichael Niewöhner
2021-08-24soc/intel: Add TGL-H CPUIDJeremy Soller
2021-08-16soc/intel/common/block/cpu: Introduce CAR_HAS_L3_PROTECTED_WAYS KconfigSubrata Banik
2021-08-15soc/intel/common: Calculate and configure SF Mask 1Subrata Banik
2021-08-15soc/intel/common: Calculate and configure SF Mask 2Subrata Banik
2021-08-09soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpusMAULIK V VAGHELA
2021-07-24soc/intel/common/block: Add space before comment delimiterSubrata Banik
2021-07-14src: use mca_clear_status function instead of open codingFelix Held
2021-07-14soc/intel/common: Use SPR for backing up data way and eviction maskSubrata Banik
2021-07-14soc/intel/common/block/cpu/cpulib: use mca_get_bank_count()Felix Held
2021-07-14include/cpu/x86/msr: introduce IA32_MC_*(x) macrosFelix Held
2021-06-26soc/intel/cache_as_ram.S: Fix CAR issues with BootguardArthur Heymans
2021-06-24soc/intel/cache_as_ram.S: Fix SOC_INTEL_APOLLOLAKEArthur Heymans
2021-06-24soc/intel/cache_as_ram.S: Add macro to detect bootguard nemArthur Heymans
2021-06-22soc/intel/car: Add support for bootguard CARArthur Heymans
2021-06-22soc/intel/common/cache_as_ram.S: Add macro to clear CARArthur Heymans
2021-06-22soc/intel/common/cache_as_ram.S: Add macro to find a free MTRRArthur Heymans