coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2017-07-13	soc/intel: add IS_ENABLED() around Kconfig symbol references	Martin Roth
2017-03-28	chromeos / broadwell / jecht: Make save_chromeos_gpios() jecht-specific	Julius Werner
2017-03-17	soc/intel/broadwell: Fix other issues detected by checkpatch	Lee Leahy
2017-03-17	soc/intel/broadwell: Fix {}, () and conditional issues	Lee Leahy
2017-03-17	soc/intel/broadwell: Fix spacing issues detected by checkpatch	Lee Leahy
2016-12-01	romstage_handoff: remove code duplication	Aaron Durbin
2016-10-31	lib/prog_loaders: use common ramstage_cache_invalid()	Aaron Durbin
2016-07-15	soc/intel/broadwell: use common Intel ACPI hardware definitions	Aaron Durbin
2016-06-29	intel romstage: Use run_ramstage()	Kyösti Mälkki
2015-10-31	tree: drop last paragraph of GPL copyright header	Patrick Georgi
2015-09-24	coreboot: move TS_END_ROMSTAGE to one spot	Aaron Durbin
2015-09-23	chromeos: vboot and chromeos dependency removal for sw write protect state	Paul Kocialkowski
2015-06-23	broadwell: fix typo	Patrick Georgi
2015-05-27	Move TPM code out of chromeos	Vladimir Serbinenko
2015-05-21	Remove address from GPLv2 headers	Patrick Georgi
2015-04-30	chromeos: Add missing headers	Patrick Georgi
2015-04-22	coreboot: common stage cache	Aaron Durbin
2015-04-21	broadwell: Implement Recovery Button	Ryan Lin
2015-04-18	broadwell: add ROM stage pre console init call back	Wenkai Du
2015-04-07	broadwell: Change all SoC headers to <soc/headername.h> system	Julius Werner
2015-03-27	broadwell: Read and save HSIO version from ME in romstage	Duncan Laurie
2015-01-14	baytrail broadwell: Use timestamps internal stash	Kyösti Mälkki
2015-01-05	timestamps: Switch from tsc_t to uint64_t	Stefan Reinauer
2014-12-31	broadwell: Preparations for building	Marc Jones
2014-10-22	broadwell: ACPI, romstage, and other updates	Duncan Laurie
2014-10-22	broadwell: add new intel SOC	Duncan Laurie