diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2015-03-06 23:17:33 -0600 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-04-22 17:55:08 +0200 |
| commit | bd74a4b2d25268f7035a4478da31f27baac2aecc (patch) | |
| tree | 56740c02fe396df8ccf9fc2e7401542deeebf453 /src/soc/intel/broadwell/romstage/romstage.c | |
| parent | cac50506238507328b8ea0f4abd458869803e6c2 (diff) | |
coreboot: common stage cache
Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.
Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/intel/broadwell/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index bf9e2ed3e9..1741ae6b82 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -25,11 +25,12 @@ #include <arch/stages.h> #include <arch/early_variables.h> #include <console/console.h> +#include <cbfs.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> #include <elog.h> -#include <ramstage_cache.h> #include <romstage_handoff.h> +#include <stage_cache.h> #include <timestamp.h> #include <soc/me.h> #include <soc/pei_data.h> @@ -142,7 +143,7 @@ void asmlinkage romstage_after_car(void) while (1); } -void ramstage_cache_invalid(struct ramstage_cache *cache) +void ramstage_cache_invalid(void) { #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE /* Perform cold reset on invalid ramstage cache. */ |