diff options
| author | Julius Werner <jwerner@chromium.org> | 2014-10-20 13:46:39 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-07 18:23:23 +0200 |
| commit | 4ee4bd5bb000b5c78e3d4a3f0113fe1e46e44851 (patch) | |
| tree | b784e37198840e63eb5dacc5aa5611543d06b5d0 /src/soc/intel/broadwell/romstage/romstage.c | |
| parent | 18ea2d3fbdf89f60a74dc8aabfdb2aa4d3475754 (diff) | |
broadwell: Change all SoC headers to <soc/headername.h> system
This patch aligns broadwell to the new SoC header include scheme.
BUG=None
TEST=Tested with whole series. Compiled Auron and Samus.
Change-Id: I0cb6aa3d17ce28890e586be1c2c7ad16d91dd925
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 23bcaa8110c4b63999c6ebf370045e9bef87ce6e
Original-Change-Id: I613ec0e2b970c75d1f8f7d9bb454bcf11abc78f0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/224507
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/9364
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/soc/intel/broadwell/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index ff5918a021..31d4f889bd 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -31,12 +31,12 @@ #include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> -#include <broadwell/me.h> -#include <broadwell/pei_data.h> -#include <broadwell/pm.h> -#include <broadwell/reset.h> -#include <broadwell/romstage.h> -#include <broadwell/spi.h> +#include <soc/me.h> +#include <soc/pei_data.h> +#include <soc/pm.h> +#include <soc/reset.h> +#include <soc/romstage.h> +#include <soc/spi.h> /* Entry from cache-as-ram.inc. */ void * asmlinkage romstage_main(unsigned long bist, |