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2021-09-25soc/intel/alderlake: Use intel_microcode_find() to locate ucode.binSubrata Banik
`intel_microcode_find()` function uses cached ucode data hence it would avoid locating ucode.bin from CBFS while passing ucode.bin pointer to FSP. Change-Id: I8f92c9f20dfb055c19c6996e601c8c24767aecb7 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24soc/intel/alderlake: Switch to using device pointersFurquan Shaikh
This change replaces the device tree walks with device pointers by using alias for tcss_usb3_port* devices. Change-Id: I65d9c83a9d0aab5a42f5a7cc6df98a154e79d16a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57848 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-24soc/intel/alderlake: add MaxDramSpeed configCasper Chang
This change add MaxDramSpeed for variants usage to config dram speed. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: Iba0fae0ab4ff0121dc63af792458492eeb21ec2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-23mb/google/brya: Migrate brya to use SPD files under spd/Reka Norman
SPD files are being moved from the soc and mainboard directories to a centralised spd/ directory. This change migrates all brya variants to use this new location. The contents of the new SPDs are identical, only their file paths have changed. The variant Makefile.inc and dram_id.generated.txt files were generated using the part_id_gen tool. E.g. for anahera: util/spd_tools/bin/part_id_gen \ ADL \ lp4x \ src/mainboard/google/brya/variants/anahera/memory \ src/mainboard/google/brya/variants/anahera/memory/mem_parts_used.txt BUG=b:191776301 TEST=Check that each variant's coreboot.rom is the same with and without this change. Built using: abuild -p none -t google/brya -a -x --timeless Change-Id: I08efe1d75438c81161d9b496af2fa30ce6f59ade Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-22soc/intel/alderlake: Drop unused HECI_DISABLE_USING_SMM KconfigSubrata Banik
Earlier generation platform used `HeciEnabled` chip config (set to 0) and HECI_DISABLE_USING_SMM Kconfig to make the CSE function disable at the end of the post. `HeciEnabled` chip config remains enabled in all latest generation platforms hence drop HECI_DISABLE_USING_SMM Kconfig selection from SoC Kconfig as CSE remains default enabled. BUG=b:200644229 TEST=No functional impact during boot as CSE (B:0, D:0x16, F:0) device is listed with `lspci`. Change-Id: I5278e5c2e015b91bb3df3a3c73a6c659a56794b5 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-09-20soc/intel/{common,tgl,adl}: guard TME Kconfig option by SoC supportMichael Niewöhner
Currently, Intel TME (Total Memory Encryption) can be enabled regardless of SoC support. Add a Kconfig to guard the option depending on actual support. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ia20152bb0fc56b0aec3019c592dd6d484829aefe Reviewed-on: https://review.coreboot.org/c/coreboot/+/57762 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-09-16vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_mainHsuan Ting Chen
vboot_reference is introducing a new field (ctx) to store the current boot mode in crrev/c/2944250 (ctx->bootmode), which will be leveraged in both vboot flow and elog_add_boot_reason in coreboot. In current steps of deciding bootmode, a function vb2ex_ec_trusted is required. This function checks gpio EC_IN_RW pin and will return 'trusted' only if EC is not in RW. Therefore, we need to implement similar utilities in coreboot. We will deprecate vb2ex_ec_trusted and use the flag, VB2_CONTEXT_EC_TRUSTED, in vboot, vb2api_fw_phase1 and set that flag in coreboot, verstage_main. Also add a help function get_ec_is_trusted which needed to be implemented per mainboard. BUG=b:177196147, b:181931817 BRANCH=none TEST=Test on trogdor if manual recovery works Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org> Change-Id: I479c8f80e45cc524ba87db4293d19b29bdfa2192 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57048 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-16drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling methodSubrata Banik
FspMultiPhaseSiInit API was introduced with FSP 2.2 specification onwards. EnableMultiPhaseSiliconInit is an arch UPD also introduced as part of FSP 2.2 specification to allow calling FspMultiPhaseSiInit API. However, some platforms adhere to the FSP specification but don't have arch UPD structure, for example : JSL, TGL and Xeon-SP. Out of these platforms, TGL supports calling of FspMultiPhaseSiInit API and considered EnableMultiPhaseSiliconInit as a platform-specific UPD rather than an arch UPD to allow calling into FspMultiPhaseSiInit API. It is important to ensure that the UPD setting and the callback for MultiPhaseInit are kept in sync, else it could result in broken behavior e.g. a hang is seen in FSP if EnableMultiPhaseSiliconInit UPD is set to 1 but the FspMultiPhaseSiInit API call is skipped. This patch provides an option for users to choose to bypass calling into MultiPhaseSiInit API and ensures the EnableMultiPhaseSiliconInit UPD is set to its default state as `disable` so that FSP-S don't consider MultiPhaseSiInit API is a mandatory entry point prior to calling other FSP API entry points. List of changes: 1. Add `FSPS_HAS_ARCH_UPD` Kconfig for SoC to select if `FSPS_ARCH_UPD` structure is part of `FSPS_UPD` structure. 2. Drop `soc_fsp_multi_phase_init_is_enable()` from JSL and Xeon-SP SoCs, a SoC override to callout that SoC doesn't support calling MultiPhase Si Init is no longer required. 3. Add `FSPS_USE_MULTI_PHASE_INIT` Kconfig for SoC to specify if SoC users want to enable `EnableMultiPhaseSiliconInit` arch UPD (using `fsp_fill_common_arch_params()`) and execute FspMultiPhaseSiInit() API. 4. Presently selects `FSPS_USE_MULTI_PHASE_INIT` from IA TCSS common code. 5. Add `fsp_is_multi_phase_init_enabled()` that check applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API to honor SoC users' decision. 6. Drop `arch_silicon_init_params()` from SoC as FSP driver (FSP 2.2) would check the applicability of MultiPhase Si Init prior calling FspMultiPhaseSiInit() API. Additionally, selects FSPS_HAS_ARCH_UPD for Alder Lake as Alder Lake FSPS_UPD structure has `FSPS_ARCH_UPD` structure and drops `arch_silicon_init_params()` from SoC `platform_fsp_silicon_init_params_cb()`. Skip EnableMultiPhaseSiliconInit hardcoding for Tiger Lake and uses the fsp_is_multi_phase_init_enabled() function to override EnableMultiPhaseSiliconInit UPD prior calling MultiPhaseSiInit FSP API. TEST=EnableMultiPhaseSiliconInit UPD is getting set or reset based on SoC user selects FSPS_USE_MULTI_PHASE_INIT Kconfig. Change-Id: I019fa8364605f5061d56e2d80b20e1a91857c423 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-16soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_TCSS at SoC levelSubrata Banik
This patch selects SOC_INTEL_COMMON_BLOCK_TCSS from Alder Lake SoC Kconfig and drops SOC_INTEL_COMMON_BLOCK_TCSS Kconfig selection from specific mainboard (brya) to ensure all Alder Lake mainboards can make use of common TCSS block. BUG=b:187385592 TEST=Type-C pendrive/Gen-2 SSD detected as Super speed. Change-Id: I85f6a967eb34ea760418131a9586bfdeb13c9b5d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57505 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-16soc/intel/alderlake: Add igd deviceWisley Chen
Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic can generate device in GFX0 scope in ssdt. BUG=b:198188272 TEST=emerge-brya coreboot and check ssdt. Change-Id: Id0c50254a8a25b47368e932c99243f4f02250b82 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-10soc/intel/alderlake: Align board type as per FSP v2347_00Ronak Kanabar
This patch adds new board type BOARD_TYPE_ULT_ULX_T4 and changes BOARD_TYPE_SERVER value to 8. BUG=b:199359579 BRANCH=None TEST=Build and boot brya Change-Id: I48eb0785a209499ee0d90bd541376d9bbacf2390 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-09-10soc/intel/alderlake: Switch to runtime generation of Intel Power EngineTim Wawrzynczak
The pep.asl file is being obsoleted by runtime generation, therefore switch alderlake boards to this method. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I617bc3d1c3cf4ac6b6cbbd790dcf62e731024834 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/alderlake: Set LpmStateEnableMask UPDTim Wawrzynczak
Use the get_supported_lpm_states() function to set the respective FSP UPD. TEST=with patchtrain on brya0, /sys/kernel/debug/pmc_core/substate_requirements shows only the substates that are applicable to the design (S0i2.0, S0i3.0). Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-10soc/intel/alderlake: Add get_adl_cpu_type functionTim Wawrzynczak
This function searches the known MCH device IDs for Alder Lake and returns the appropriate enum value representing ADL-P, ADL-M, ADL-S, or unknown. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I26354b340e0c5f15ba246c1cb831d7feaf62d2ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/57151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-09soc/intel/alderlake: Change VBOOT_HASH_BLOCK_SIZE to 4 KiBMAULIK V VAGHELA
Default VBOOT_HASH_BLOCK_SIZE is 1 KiB and increasing it to 4 KiB helps in improving overall boot time since it reduces hashing and body loading time. Increasing it over 4 KiB doesn't result in significant improvement, thus keeping the value at 4 KiB as of now. Timing data: Note that before Data is with 1 KiB block size. |------------------------------------------------------| | Stage | Block Size | Before | After | |finished loading body| 4 KiB | 205,187 | 189,947 | |finished loading body| 8 KiB | 205,187 | 188,708 | |finished loading body| 16 KiB | 205,187 | 188,085 | |finished loading body| 32 KiB | 205,187 | 187,793 | |------------------------------------------------------| BUG=b:188577893 BRANCH=None TEST=Boot time for Brya improves by 20 - 25 msec Change-Id: I9222761c7d58e4a370d3a41c651b6c169599d792 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-09soc/intel/alderlake: Enable Irms UPD for ADLRonak Kanabar
This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit is set to non zero. It results VR TDC Input current to be treated as it is root mean square. This change also optimizes the check of TdcTimeWindow and TdcCurrentLimit for TdcEnable UPD. BRANCH=None TEST=Build and boot brya with debug FSP and verify Irms UPD value from logs Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-09-08cpu/x86/tsc: Deduplicate Makefile logicAngel Pons
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc` is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig option is enabled. Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and drop the now-redundant inclusions from platform code. Also, deduplicate the `UDELAY_TSC` guards. Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-06soc/intel/adl: Move USB4 hotplug Kconfig to commonFurquan Shaikh
This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES` that can be selected by mainboard to reserve hotplug resources for USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped from soc/intel/alderlake and instead the newly added Kconfig is now used. This new Kconfig is added so that the same config can be used across different platforms. In following changes, this Kconfig is utilized by TGL as well. Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-09-05soc/intel/alderlake: Add tpch device information under dptfSumeet Pawnikar
Add tpch device information for thermal functionality under dptf for alderlake soc based platform. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Iad8e8bc0b7a104bbe582bc477936d0d00087f1d1 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-09-03soc/intel/alderlake: set power limits dynamically for thermalSumeet Pawnikar
Set power limit values dynamically based on CPU TDP and PCI ID of SKU. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: Ic331a3debb076ef08a312a31edc1468974fd4902 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57035 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01soc/intel/alderlake: Fix processor hang while plug unplug of TBT deviceSugnan Prabhu S
Processor hang is observed while hot plug unplug of TBT device. BIOS should execute TBT PCIe RP RTD3 flow based on the value of TBT_DMA_CFG_VS_CAP_9[30]. It should skip TBT PCIe RP RTD3 flow, if BIT30 in TBT FW version is not set. BUG=b:194880254 Change-Id: Ie3577df519f64c6f7270dc5537278af76536774e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56503 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26soc/intel/alderlake: Lock PAM registers in finalizeTim Wawrzynczak
Use the support from the previous patch to have coreboot lock the PAM registers instead of the FSP when the lockdown configuration is set to coreboot. TEST=boot to OS, read PCI 0:0.0 config register 0x80, value is 0x31 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I0c3e16edeab6f85a79eb10e1477d95952b554a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-20soc/intel/adl: Update power limits for ADL-M SKUSumeet Pawnikar
Update SKU specific power limits for ADL-M as per document 643775. BUG=None BRANCH=None Change-Id: I40b9b3a508c549d940e1c2c9e8b4079695b694e6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-20soc/intel/adl: Update PCI ID for ADL-M SKUSumeet Pawnikar
Update PCI ID for ADL-M as per document 643775. BUG=None BRANCH=None Change-Id: Ia2c5ce270bc421d8a41cc4bc6ce0b51987d2aaec Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19soc/intel/alderlake: Move INTEL_CAR_NEM selection from SoC to mainboardSubrata Banik
This patch decouples the selection of eNEM feature enablement from SoC to ensure the ADLRVP does the validation first prior enabling this feature on OEM/ODM reference designs. BUG=b:168820083 TEST=No changing is being observed in .config with and without this CL. Change-Id: I709185159d9869501b1d8e8d00f6d25ec77838bf Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-19soc/intel/alderlake: set default PL4 values for different SKUsSumeet Pawnikar
Set default PL4 values for various Alder Lake CPU SKUs as per bug#191906315 comment#10. BUG=b:194745919 BRANCH=None TEST=Build FW and test on brya0 board. Change-Id: I53791badbec3c165d56f20ce0656dc15d63bab37 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56917 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-16soc/intel/alderlake: Create eNEM Kconfig for Alder LakeSubrata Banik
Alder Lake SoC specific Kconfig that internally selects all eNEM related Kconfig. CONFIG_ALDERLAKE_CAR_ENHANCED_NEM will get autoselected if platform doesn't have INTEL_CAR_NEM Kconfig selected explicitly. BUG=b:168820083 TEST=Verified CONFIG_INTEL_CAR_NEM is still enable. Change-Id: Ife1c7d2036cece4598275dfc26ed138fb46bd881 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56090 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/alderlake: Clean up FSP chipset lockdown configurationFelix Singer
Use a variable to store if the FSP should be responsible for the chipset lockdown and use it for setting related configuration options. Thus, get rid of that if-else-clause. Change-Id: Ia6485bde5b33af067dfb15ca410a164e288b76b2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-08-12soc/intel/alderlake: Configure the SKU specific parameters for VR domainsV Sowmya
This patch configures the SKU specific power delivery parameters for the VR domains. +--------------+-------+-------+-------+-------+-----------+--------+ | SKU |Setting| AC LL | DC LL |ICC MAX|TDC Current|TDC Time| | | |(mOhms)|(mOhms)| (A) | (A) | (msec)| +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 682(45W)| IA | 2.3 | 2.3 | 160 | 57 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 57 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 482(28W)| IA | 2.3 | 2.3 | 109 | 40 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 50 | 40 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ |ADL-P 282(15W)| IA | 2.8 | 2.8 | 80 | 20 | 28000 | + +-------+-------+-------+-------+-----------+--------+ | | GT | 3.2 | 3.2 | 40 | 20 | 28000 | +--------------+-------+-------+-------+-------+-----------+--------+ These config values are generated iPDG application with ADL-P platform package tool and supports 15W/28W/45W SKU's. RDC Kit ID for the iPDG tools, * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:195033556 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I434fd30b5bce3bfab5a5800a30317aaa04d9926a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56325 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-12soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADLV Sowmya
This patch updates the VccIn Aux Imon IccMax for ADL-P to SOC SKU specific values from the FSP default value 160. * ADL-P 682(45W) = 137. * ADL-P 482(28W) = 128. * ADL-P 282(15W) = 128. These config values are generated iPDG application with ADL-P platform package tool and supports 15W/28W/45W SKU's. RDC Kit ID for the iPDG tools, * Intel(R) Platform Design Studio Installer: 610905. * Intel(R) Platform Design Studio - Platform ADL-P (Partial): 627345. * Intel(R) Platform Design Studio - Platform ADL-P (Full): 630261. BUG=b:195033556 Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I6c159035cba781d3661a0a0cef16f9591a583912 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56176 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-11soc/intel/alderlake: Implement report_cache_info() functionSubrata Banik
Make use of deterministic cache helper functions from Alder Lake SoC code to print useful information during boot as below: Cache: Level 3: Associativity = 12 Partitions = 1 Line Size=64 Sets=16384 Cache size = 12 MiB Change-Id: I30a56266015d69abccb885b3f230689488ee0360 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55654 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-10mb/*/{brya,adlrvp}: move cpu_cluster static configuration to chipset.cbMAULIK V VAGHELA
For mainboard devicetree, it always have definition for enabling cpu_cluster 0 which is required for all the variants. Since it is SoC related settings, it's better to keep in chipset.cb as a common setting for all the mainboards using the same SoC. BUG=None BRANCH=None TEST=Change has no functional impact on the brya board. Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56853 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05soc/intel/alderlake: Add GFx Device ID 0x46aaBora Guvendik
This CL adds support for new ADL-M graphics Device ID 0x46aa. TEST=boot to OS Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: Ib24b494b0eedad447f3b2a3d1d80c9941680c25d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56775 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-08-04Move post_codes.h to commonlib/console/Ricardo Quesada
Move post_codes.h from include/console to commonlib/include/commonlib/console. This is because post_codes.h is needed by code from util/ (util/ code in different commit). Also, it sorts the #include statements in the files that were modified. BUG=b:172210863 Signed-off-by: Ricardo Quesada <ricardoq@google.com> Change-Id: Ie48c4b1d01474237d007c47832613cf1d4a86ae1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56403 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-03soc/intel/*: Allow configuring 8254 timer via CMOSSean Rhodes
Currently, the `USE_LEGACY_8254_TIMER` Kconfig option is the only way to enable or disable the legacy 8254 timer. Add the `legacy_8254_timer` CMOS option to allow enabling and disabling the 8254 timer without having to rebuild and reflash coreboot. If options are not enabled or the option is missing in cmos.layout, the Kconfig setting is used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic82c7f25cdf6587de5c40f59441579cfc92ff2f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-07-28util/spd_tools/lp4x: Add new memory parts and generate SPDsDavid Wu
This change adds the following memory parts to LP4x global list and generates SPDs using gen_spd.go for ADL: 1. H54G46CYRBX267 2. H54G56CYRBX247 3. K4U6E3S4AB-MGCL 4. K4UBE3D4AB-MGCL BUG=b:194686484 b:194765811 TEST=build. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If85088f843ab11cc531a3975b5cac3e36b573970 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol more than once. This is done in `src/Kconfig`, along with its prompt. Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-20soc/intel/alderlake: Add support for I2C6 and I2C7Varshit B Pandya
As per the EDS revision 1.3 add support for I2C6 and I2C7. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: Id918d55e48b91993af9de8381995917aef55edc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55996 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-19soc/intel/common: Rename kconfig PMC_EPOCLean Sheng Tan
Rename PMC_EPOC to SOC_INTEL_COMMON_BLOCK_PMC_EPOC to maintain common naming convention. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: If8a264007bbb85a44bbdfa72115eb687c32ec36e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17soc/intel/alderlake: Select INTEL_GMA_OPREGION_2_1Meera Ravindranath
Alder Lake supports IGD Opregion version 2.1. BUG=b:190019970 BRANCH=None Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I95a6f3df185003a4e38faa920f867ace0b97ab2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-17soc/intel/alderlake: Make use of `cpu/intel/cpu_ids.h'Subrata Banik
Remove inclusion of mp_init.h for getting CPUIDs and use dedicated cpu_ids.h file in SoC directory. Change-Id: Ib62ad6a5381d346011fbc838dcd64b095fccd67b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-15soc/intel/alderlake: Add virtual GPIOs for community 1Maulik V Vaghela
Alder Lake SoC has virtual GPIOs for community 1 which was being programmed by FSP and hence was skipped by coreboot. As part of moving most of the GPIO programming to coreboot, we're skipping this programming in FSP now. TEST=Check register offset to see if programming is correct. Change-Id: I4d48553d14465df50e5aaaf27ab26c6a1b70d4cf Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55270 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/intel/alderlake: Use `is_devfn_enabled()` for Crashlog UPDsSubrata Banik
Enable FSP Crashlog UPDs if SA_DEVFN_TMT is enabled and SOC_INTEL_CRASHLOG is selected by the SoC user. Change-Id: I0244e2a3f9c000a5c6ecdade1419aa47f51b1e80 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56298 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-14soc/intel/alderlake: Add GFx Device ID 0x46a6Maulik V Vaghela
This CL adds support for new ADL graphics Device ID 0x46a6. TEST=Build and boot Adlrvp board Change-Id: I8ca875c7faf2997d207aff9e292f94a3b6311e94 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56026 Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13soc/intel/alderlake: Implement WA for DDR5 DIMM modulesMeera Ravindranath
The coreboot SMBus driver requires additional changes to accomodate the DDR5 EEPROM read which has resulted in a broken code flow for boot. This CL serves as a temp WA to let FSP perform the SPD read for DDR5 and pass SPD addresses to FSP UPD array. BUG=b:180458099 TEST=Build and boot DDR5 adlrvp to OS Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I9998bfcd12b81c11fcc9f791da2a27d3c788e48a Reviewed-on: https://review.coreboot.org/c/coreboot/+/50996 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-13soc/intel/alderlake: Add (and fix) devices in IRQ tableTim Wawrzynczak
Some devices were missing from the IRQ table, and this lack of IRQ programming for the devices (although unused), was causing S0ix entry to fail. BUG=b:176858827 TEST=suspend_stress_test -c10 passes, EC observes SLP_S0IX# toggle correctly upon entry/exit from S0ix Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia7612ee008842ba2b8dcd36deb201f4f26130660 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-07-12soc/intel/alderlake: Increase PRERAM_CBMEM_CONSOLE_SIZE to 8KBSubrata Banik
This patch increases PRERAM_CBMEM_CONSOLE_SIZE from 5KB to 8KB to fix cbmem buffer overflow issue. Test=Boot ADLRVP and check cbmem -c | grep 'CBFS: Found' lists all stages. Change-Id: I38fd74c2edd71ce9f6c08db9dacb18e553745877 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-07-12soc/intel/alderlake: Add missing devices to pci_devs.hTim Wawrzynczak
There were some devices missing from pci_devs.h: 1) GNA 2) I2C6 and I2C7 3) UART3, UART4, UART5, UART6 4) UFS 5) GSPI4, GSPI5, GSPI6 BUG=b:176858827 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I2b9f8cceb4bd0c77fc43ef2e48190dd736a84ad8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56172 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-12soc/intel/alderlake: Set max Pkg C-states to AutoV Sowmya
This patch configures max Pkg C-state to Auto which limits the max C-state to deep C-state Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Iab92eaadad3f17ed8dddc4f383d6eeaab8c9ea6e Reviewed-on: https://review.coreboot.org/c/coreboot/+/55706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-08soc/intel/alderlake: Avoid NULL pointer deferenceJohn Zhao
Coverity detects dereference pointers req and res that are NULL when calling the pmc_send_ipc_cmd function. This change prevents NULL pointers dereference. Found-by: Coverity CID 1458077, 1458078 TEST=None Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I151157e7a9a90c43075f431933ac44f29fd25127 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-05soc/intel/alderlake: Add support to update the FIVR configsV Sowmya
This patch adds the supports to update the optimal FIVR configurations for external voltage rails via devicetree. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: Icf6c74bda5a167abf63938ebed6affc6b31c76f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55702 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-05soc/intel/alderlake: Correct Bus and Device of Touch Host ControllerVarshit B Pandya
Correct Bus and Device for THC0 and THC1 Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I41858ea156c8258ea0e7be9e2f67fb0e24144c80 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-07-02src: Introduce `ARCH_ALL_STAGES_X86`Angel Pons
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically select the per-stage arch options. Subsequent commits will leverage this to allow choosing between 32-bit and 64-bit coreboot where all stages are x86. AMD Picasso and AMD Cezanne are the only exceptions to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set the per-stage arch options accordingly. Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-07-02soc/intel/alderlake: Add USB TCSS enablementBernardo Perez Priego
In order to detect USB Type C device port as Super Speed, we need to set corresponding bit in UPD UsbTcPortEn. This patch will use device path to determine which port should be enabled. BUG=b:184324979 Test=Boot board, USB Type C must be functional and operate at Super Speed. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I7da63f21d51889a888699540f780cb26b480c26d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01soc/intel/alderlake: Enable energy efficiency turbo modeV Sowmya
This patch enables the energy efficiency turbo mode. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I2d76c948bdc9c208f5728e305b3034fcede6f4bf Reviewed-on: https://review.coreboot.org/c/coreboot/+/55705 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-01soc/intel: Refactor `xdci_can_enable()` functionAngel Pons
The same pattern appears on all `xdci_can_enable()` call sites. Move the logic inside the function and take the xDCI devfn as parameter. Change-Id: I94c24c10c7fc7c5b4938cffca17bdfb853c7bd59 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55790 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-07-01soc/intel/alderlake: Select VBOOT_X86_SHA256_ACCELERATION configSubrata Banik
By enabling the flag alderlake platform will use hardware sha instruction instead of software implementation for sha256. This will speed up firmware verification especially on low-performance device. Change-Id: Ie8ab02360fdceafab257e9a301e6a89d3a22c3ae Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30soc/intel/alderlake: Send End-of-Post message to CSETim Wawrzynczak
This is done to ensure the CSE will not execute any pre-boot commands after it receives this command. Verified EOP and error recovery sequence from Intel doc#627331. TEST=on brya, autotest firmware_CheckEOPState confirms ME is in post-boot state Change-Id: Iee8c29f81d5d04852ae3f16dc8a9ff0fa59f056a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-06-30soc/intel/common: Move PMC EPOC related code to Intel common codeLean Sheng Tan
Move PMC EPOC related code to intel/common/block because it is generic for most Intel platforms and ADL, TGL & EHL use it. Add a kconfig 'PMC_EPOC' to guard this common EPOC code. The PMC EPOC register indicates which external crystal oscillator is connected to the PCH. This frequency is important for determining the IP clock of internal PCH devices. Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Change-Id: Ib5fd3c4a648964678ee40ed0f60ca10fe7953f56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55565 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-30src: Move `select ARCH_X86` to platformsAngel Pons
To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware, have platforms select `ARCH_X86` directly instead of through per-stage Kconfig options, effectively reversing the dependency order. Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-06-29soc/intel/alderlake: Enable support for common IRQ blockTim Wawrzynczak
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch allows ADL boards to dynamically assign PCI IRQs. This means not relying on FSP defaults, which eliminates the problem of PCI IRQs interfering with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC routing. BUG=b:176858827 TEST=brya0, grep 'IO-APIC' /proc/interrupts (compressed to fit) 0: 36 0 0 0 0 0 0 0 IO-APIC 2-edge time 1: 0 0 9 0 0 0 0 0 IO-APIC 1-edge i804 8: 0 0 0 0 0 0 0 0 IO-APIC 8-edge rtc0 9: 0 21705 0 0 0 0 0 0 IO-APIC 9-fasteoi acpi 14: 0 0 0 0 0 0 0 0 IO-APIC 14-fasteoi INTC 18: 0 0 0 0 0 0 0 0 IO-APIC 18-fasteoi inte 20: 0 0 0 0 0 0 0 394 IO-APIC 20-fasteoi idma 23: 2280 0 0 0 0 0 0 0 IO-APIC 23-fasteoi idma 26: 0 0 26 0 0 0 0 0 IO-APIC 26-fasteoi idma 27: 0 0 0 6 0 0 0 0 IO-APIC 27-fasteoi idma 28: 0 0 0 0 0 0 0 0 IO-APIC 28-fasteoi idma 29: 0 0 0 0 25784 0 0 0 IO-APIC 29-fasteoi idma 30: 0 0 0 0 0 0 0 0 IO-APIC 30-fasteoi idma 31: 0 0 0 0 0 0 226 0 IO-APIC 31-fasteoi idma 77: 0 0 0 0 0 2604 0 0 IO-APIC 77-edge cr50 100: 0 0 0 0 0 0 0 0 IO-APIC 100-fasteoi ELAN 103: 0 0 0 0 0 0 0 0 IO-APIC 103-fasteoi chro abbreviated _PRT dump: If (PICM) Package (){0x0002FFFF, 0, 0, 0x10}, Package (){0x0004FFFF, 0, 0, 0x11}, Package (){0x0005FFFF, 0, 0, 0x12}, Package (){0x0006FFFF, 0, 0, 0x13}, Package (){0x0006FFFF, 1, 0, 0x14}, Package (){0x0007FFFF, 0, 0, 0x15}, Package (){0x0007FFFF, 1, 0, 0x16}, Package (){0x0007FFFF, 2, 0, 0x17}, Package (){0x0007FFFF, 3, 0, 0x10}, Package (){0x000DFFFF, 0, 0, 0x11}, Package (){0x0012FFFF, 0, 0, 0x18}, Package (){0x0012FFFF, 1, 0, 0x19}, Package (){0x0014FFFF, 0, 0, 0x12}, Package (){0x0014FFFF, 1, 0, 0x13}, Package (){0x0015FFFF, 0, 0, 0x1A}, Package (){0x0015FFFF, 1, 0, 0x1B}, Package (){0x0015FFFF, 2, 0, 0x1C}, Package (){0x0015FFFF, 3, 0, 0x1D}, Package (){0x0016FFFF, 0, 0, 0x14}, Package (){0x0016FFFF, 1, 0, 0x15}, Package (){0x0016FFFF, 2, 0, 0x16}, Package (){0x0016FFFF, 3, 0, 0x17}, Package (){0x0017FFFF, 0, 0, 0x10}, Package (){0x0019FFFF, 0, 0, 0x1E}, Package (){0x0019FFFF, 1, 0, 0x1F}, Package (){0x0019FFFF, 2, 0, 0x20}, Package (){0x001CFFFF, 0, 0, 0x10}, Package (){0x001CFFFF, 1, 0, 0x11}, Package (){0x001CFFFF, 2, 0, 0x12}, Package (){0x001CFFFF, 3, 0, 0x13}, Package (){0x001DFFFF, 0, 0, 0x10}, Package (){0x001DFFFF, 1, 0, 0x11}, Package (){0x001DFFFF, 2, 0, 0x12}, Package (){0x001DFFFF, 3, 0, 0x13}, Package (){0x001EFFFF, 0, 0, 0x14}, Package (){0x001EFFFF, 1, 0, 0x15}, Package (){0x001EFFFF, 2, 0, 0x16}, Package (){0x001EFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 1, 0, 0x15}, Package (){0x001FFFFF, 2, 0, 0x16}, Package (){0x001FFFFF, 3, 0, 0x17}, Package (){0x001FFFFF, 0, 0, 0x14}, Else Package (){0x0002FFFF, 0, 0, 0x0B}, Package (){0x0004FFFF, 0, 0, 0x0A}, Package (){0x0005FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 0, 0, 0x0B}, Package (){0x0006FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 0, 0, 0x0B}, Package (){0x0007FFFF, 1, 0, 0x0B}, Package (){0x0007FFFF, 2, 0, 0x0B}, Package (){0x0007FFFF, 3, 0, 0x0B}, Package (){0x000DFFFF, 0, 0, 0x0A}, Package (){0x0014FFFF, 0, 0, 0x0B}, Package (){0x0014FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 0, 0, 0x0B}, Package (){0x0016FFFF, 1, 0, 0x0B}, Package (){0x0016FFFF, 2, 0, 0x0B}, Package (){0x0016FFFF, 3, 0, 0x0B}, Package (){0x0017FFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 0, 0, 0x0B}, Package (){0x001CFFFF, 1, 0, 0x0A}, Package (){0x001CFFFF, 2, 0, 0x0B}, Package (){0x001CFFFF, 3, 0, 0x0B}, Package (){0x001DFFFF, 0, 0, 0x0B}, Package (){0x001DFFFF, 1, 0, 0x0A}, Package (){0x001DFFFF, 2, 0, 0x0B}, Package (){0x001DFFFF, 3, 0, 0x0B}, Package (){0x001EFFFF, 0, 0, 0x0B}, Package (){0x001EFFFF, 1, 0, 0x0B}, Package (){0x001EFFFF, 2, 0, 0x0B}, Package (){0x001EFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 1, 0, 0x0B}, Package (){0x001FFFFF, 2, 0, 0x0B}, Package (){0x001FFFFF, 3, 0, 0x0B}, Package (){0x001FFFFF, 0, 0, 0x0B}, dmesg shows no GSI or PCI errors, TPM & touchpad IRQs still work Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I1e7a708183ac4170b28da9565137fa2f5088a7eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/54683 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-28soc/intel: Drop casts around `soc_read_pmc_base()`Angel Pons
The `soc_read_pmc_base()` function returns an `uintptr_t`, which is then casted to a pointer type for use with `read32()` and/or `write32()`. But since commit b324df6a540d154cc9267c0398654f9142aae052 (arch/x86: Provide readXp/writeXp helpers in arch/mmio.h), the `read32p()` and `write32p()` functions live in `arch/mmio.h`. These functions use the `uintptr_t type for the address parameter instead of a pointer type, and using them with the `soc_read_pmc_base()` function allows dropping the casts to pointer. Change-Id: Iaf16e6f23d139e6f79360d9a29576406b7b15b07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-06-25soc/intel/alderlake: Fix the typo for FSP_S_CONFIG paramV Sowmya
This patch fixes the typo introduced in commit b03cadf for renaming FSP_S_CONFIG param name to s_cfg. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I0a9b500e528c68033008f3f8955d6c9c9ba8a737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-06-25soc/intel/alderlake: Update s0ix cstate tableBernardo Perez Priego
Cstate C7 is not supported in ADL, replacing this unsupported state with C6 in the s0ix cstate table. BUG=None TEST=Boot device to OS. Print supported CStates and latencies. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I471f71481d337e3fafa4acab7fe8a39677c8710c Reviewed-on: https://review.coreboot.org/c/coreboot/+/55734 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24soc/intel/alderlake: Update mainboard_memory_init_params() argumentSubrata Banik
This patch updates mainboard_memory_init_params() function argument from FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params() function don't need to override anything other than FSP_M_CONFIG UPDs hence passing config block alone rather passing entire FSP-M UPD structure. Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24soc/intel/alderlake: Refactor soc_silicon_init_params functionSubrata Banik
This patch create separate helper functions to fill-in required FSP-S UPDs as per IP initialization categories. This would help to increase the code readability and in future meaningful addition of FSP-S UPDs is possible rather adding UPDs randomly. TEST=FSP-S UPD dump shows no change without and with this code change. Change-Id: Iba51aebc74456449e24e51e2f309f14f951464a0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55233 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-24soc/intel/alderlake: Rename FSP_S_CONFIG variable from params to s_cfgSubrata Banik
Align FSP-S UPD structure (FSP_S_CONFIG) variable name (s_cfg) as FSP-M UPD structure variable (m_cfg). TEST=Able to build and boot ADLRVP to ChromeOS. FSP-S UPD dump shows no change in UPD values with this CL. Change-Id: I795f733f5f0cc64d3a556a1cd401323b35ba5a23 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-24soc/intel/alderlake: Refactor platform_fsp_silicon_init_params_cb functionSubrata Banik
Align platform_fsp_silicon_init_params_cb() function implementation with romstage/fsp_params.c file platform_fsp_memory_init_params_cb() as: |- Override FSP-S Arch UPD(s) using arch_silicon_init_params(). |- Override FSP-S SoC UPDs using soc_silicon_init_params(). |- Override FSP-S Mainboard UPDs using mainboard_silicon_init_params(). TEST=FSP-S UPD dump shows no change without and with this code change. Change-Id: I4cf0b8423fb4038a7feddd97ff585027b3012605 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55293 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-23soc/intel/alderlake: Use devfn_disable() function for XDCISubrata Banik
Use devfn_disable() for disabling a PCI device rather than using `dev->enabled = 0`. Also, use is_devfn_enabled() to get the device current state prior updating the FSP-S UPD for XDCI. TEST=FSP-S disabled XDCI when `xdci_can_enable` returns 0 and XDCI is disabled at PCI enumeration `PCI: 00:14.1: enabled 0`. Change-Id: I5e10e5d0b80986e1e73573a86a957985840fe0b3 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55727 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-21soc/intel/alderlake: Add GFx Device ID 0x46b3Meera Ravindranath
List of changes: 1. Add new GFx ID 0x46B3 into device/pci_ids.h 2. Update new GFx ID into common graphics.c 3. Add new GFx ID description into report_platform.c TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I4343c7343875eb40c2955f6f4dd98d6446852dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-06-18soc/intel/alderlake: Add TBT PCIe root ports enablementBernardo Perez Priego
Ports are enabled according to devicetree. BUG=none TEST=Boot device, TBT should be functional Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: I57e8eb13484014c17d24ad564643f0d03d11bc58 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-17soc/intel/{alderlake,tigerlake}: Fix typo in pmc.hWerner Zeh
"corredsponding" --> "corresponding" Change-Id: I0b0e5d461de29583c269896911167f8a44d84c2a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55555 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-17soc/intel/alderlake/romstage: Refactor soc_memory_init_params functionSubrata Banik
This patch create separate helper functions to fill-in required FSP-M UPDs as per IP initialization categories. This would help to increase the code readability and in future meaningful addition of FSP-M UPDs is possible rather adding UPDs randomly. TEST=FSP-M UPD dump shows no change without and with this code change. Change-Id: I5f23292fd1bd44d0cd55fbefd490b090ccd48365 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55225 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-16soc/intel/alderlake/romstage: Update display UPDs based on InternalGfxSubrata Banik
Disable all display related UPDs if IGD is not enabled as FSP don't need to perform display port initialization while IGD itself is disabled else assign UPDs based on devicetree config. TEST=Dump FSP-M display related UPDs with IGD enable and disable to ensure patch integrity. Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-16soc/intel/alderlake: Make use of is_devfn_enabled() functionSubrata Banik
1. Replace all pcidev_path_on_root() and is_dev_enabled() functions combination with is_devfn_enabled(). 2. Remove unused local variable of device structure type (struct device *). 3. Replace pcidev_path_on_root() and dev->enabled check with is_devfn_enabled() call. TEST=Able to build and boot without any regression seen on ADL. Change-Id: I92671992ec14fd2adca1635b0791ac8b456332e9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55292 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-11soc/intel/{common,alderlake}: Use generic name "Alderlake Platform"Sridhar Siricilla
Since common CPU ID between ADL-P and ADL-M CPU IDs, the patch renames all ADL-P and ADL-M Silicon CPUID macros and defines generic name "Alderlake Platform" as macro value. Also, this will avoid log ADL-M for ADL-P CPU and vice-versa. Although currently name field of "cpu_table" points to only "Alderlake Platform, but it is retained asa placeholder in future difference platforms. Please refer EDS doc# 619501 for more details. The macros are renamed as below: CPUID_ALDERLAKE_P_A0 -> CPUID_ALDERLAKE_A0 CPUID_ALDERLAKE_M_A0 -> CPUID_ALDERLAKE_A1 CPUID_ALDERLAKE_P_B0 -> CPUID_ALDERLAKE_A2 TEST=Verify boot on Brya. After change, relevent coreboot logs appear as below: CPU: ID 906a1, Alderlake Platform, ucode: 00000119 CPU: AES supported, TXT supported, VT supported MCH: device id 4601 (rev 03) is Alderlake-P PCH: device id 5181 (rev 00) is Alderlake-P SKU IGD: device id 46b0 (rev 04) is Alderlake P GT2 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ia06d2b62d4194edd4e104d49b340ac23305a4c15 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55252 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-08soc/intel/alderlake/romstage: Drop ineffective FSP-M UPD `ChHashMask`Subrata Banik
FSP-M UPD ChHashOverride is default disable hence ChHashMask doesn't take any effect. Dropping ChHashMask assignment in coreboot. TEST=Able to build and boot ADL-P LP4 RVP. FSP-M UPD dump showed both UPDs are set to default value 0. ChHashOverride: 0 ChHashMask: 0h Change-Id: Ide1c9da27ca68fd36ff5b44910cfcedfcb12f232 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55272 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-08soc/intel/alderlake: Set SaIpuEnable UPD according to devicetreeTim Wawrzynczak
The SaIpuEnable UPD is not currently being touched by coreboot; set it according to the enabled status of the corresponding devicetree node. TEST=turn ipu device on or off in devicetree, see device enumerated or not in OS, according to the devicetree setting. Change-Id: I53752f92c4b49093218cc34848727a72b63e84eb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55143 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-08soc/intel: Add Alder Lake's GT device IDSridhar Siricilla
Add Alder Lake specific graphics device ID. The document# 641765 lists the id 0x46a8. TEST=Verify boot on brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I6f36256505a3e07c6197079ea2013991e841401b Reviewed-on: https://review.coreboot.org/c/coreboot/+/55256 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-08soc/intel/alderlake: Correct TCSS XHCI Port status offsetSridhar Siricilla
The patch corrects TCSS XHCI Port status offset and CPU USB2 port count. The information is captured from the ADL-P Processor EDS Volume 2b of 2 (DOC ID:619503). BUG=None TEST=Verified boot on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I20c77d78f52277a9a979e11303cdb6cdabae7c59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55230 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-06-07cpu/x86: Default to PARALLEL_MP selectedKyösti Mälkki
Change-Id: I9833c4f6c43b3e67f95bd465c42d7a5036dff914 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-06-07soc/intel/adl: Add SKU specific power limits supportSumeet Pawnikar
Power limits (PL1 and PL2) depend on the specific SKU of the CPU. By expanding the SoC chip config power_limits_config member to an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the appropriate power limits are applied. Using this the correct set of power limits are being selected from the array based on system agent PCI ID. Based on this, chipset.cb file contains the set of power limits being used by varieties of ADL boards. These power limit values are as per document 619501. BUG=None BRANCH=None TEST=Built and verified the following console output on below boards On adlrvp (482): CPU PL1 = 28 Watts CPU PL2 = 64 Watts On adlrvp (682): CPU PL1 = 45 Watts CPU PL2 = 115 Watts On brya (282): CPU PL1 = 15 Watts CPU PL2 = 55 Watts Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
2021-06-07soc/intel/alderlake: Update ACPI device ID of IOMMaulik V Vaghela
ACPI device ID of IOM device has been changed for Alder Lake. Updating it to make it compatible with kernel TEST=ACPI ID is updated and kernel driver works as expected Cq-Depend: chromium:2936144 Change-Id: Ifdfcd0c1534e8204719e59e718688cd42e846e84 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-07soc/intel: Drop unused lpss functionsFurquan Shaikh
This change drops the following unused lpss functions and related code: * soc_lpss_controllers_list * is_dev_lpss These functions were added to determine if a controller is LPSS for performing IRQ configuration. But, these never got used and hence are being dropped. Change-Id: I27bdfbca7c199e823a0e4fdb277e3f22fb6bae7a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-06-07soc/intel/alderlake: Set Base Addresses for TBT DMA remapping enginesSridhar Siricilla
The patch configures 4KB memory region window for each of the TBT DMA remapping engine. So, the remap engines map their register set to the respective 4KB window. TEST=Verified boot on Brya Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I669255065d60d73c4bea0eeb732c4114bcc447c0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55015 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-05soc/intel/alderlake: Add IDE-R and KT device into chipset.cbSubrata Banik
Add IDE-R and KT device to chipset.cb and leave it off by default. Change-Id: Iaa51e3dc107eb3f06ad7b2aad72a6bc112999d98 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55209 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-06-04soc/intel/alderlake: Add PMC ACPI interfaceTim Wawrzynczak
This ACPI interface is required by e.g., the intel/common/pcie/rtd3 driver, which is used by some alderlake boards. BUG=b:190080798 TEST=disassemble SSDT and find \_SB.PCI0.PMC.IPCS Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I59eae47e623587d35e394c9bff21481fcad2d6b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55172 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-03soc/intel/alderlake: Add new memory parts for ADL boardsAmanda Huang
Use currently global_lp4x_mem_parts.json.txt to regenerate SPD files for LP4x memory parts that can be used with ADL-based mainboards. BUG=b:186616388 Change-Id: I5e76a887f81d432adbcfc2f8956b44f4343db5c2 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-05-30soc/intel/alderlake: Add placeholder SPD fileTim Wawrzynczak
Change-Id: I38eb4bb684c511fff5ae148091c066682e9c35cb Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-05-26soc/intel/alderlake: Update soundwire master countSugnan Prabhu S
This patch includes changes to update the soundwire master count. Change-Id: Iffaf90569c19fb5ca3ce4775cc6dc6f8093f7c52 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-26soc/intel/alderlake: Add validity for TBT firmware authenticationJohn Zhao
After Thunderbolt firmware is downloaded to IMR, its authentication validity needs to be checked. This change adds the TBT firmware IMR status register offset and its authentication valid bit for valid_tbt_auth function usage. BUG=b:188695995 TEST=Built coreboot image successfully. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I742a00b6b58c45c1261f06b06a94346ad0a74829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54888 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-25soc/intel/alderlake: Fix SA_DEVFN_CPU_PCIE6_*Tim Wawrzynczak
Change-Id: I8849f6dd2a9fdb16642de423cc82dcefd5b192ac Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54682 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-21soc/intel/common: Add Alder Lake device IDsSumeet R Pawnikar
Add Alder Lake specific Host and Graphics device IDs. As per latest document number: 619501, these IDs got an update. Change-Id: I548a903714ccc7470f1425ac67c0c66522437365 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54674 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-18soc/intel/alderlake: Add handling of GPIO_COM3 in gpio.aslMaulik V Vaghela
We were not adding power management handling of GPIO_COM3 in gpio.asl This can affect s0ix flow where platform won't go into s0ix since GPIO_COM3 is not power gated. BUG=b:188392183 BRANCH=None TEST=Platform should enter to s0ix and GPIO COMM3 should not block an entry to s0ix. Change-Id: I3f269c66bdd6337adb0d2bd29d0b7d72ced19ec4 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-18cpu/x86: Only include smm code if CONFIG_HAVE_SMI_HANDLER=yArthur Heymans
This removes the need to include this code separately on each platform. Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-05-18soc/intel/alderlake: mb/intel/sm: Add tcss codeDeepti Deshatty
Enable FSP 'MultiPhaseSilicon' init to execute tcss configure during silicon init. Type-c aux lines DC bias changes are propagated from tigerlake platform. TEST=Verified superspeed pendrive detection on coldboot. Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Change-Id: Ifce6abb0fce20e408931b904426131a42a5a4a36 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-16soc/intel/alderlake: Update meminit code due to upd changes FSP 2147 onwardsBora Guvendik
DisableDimmMc0Ch0 upds changed to DisableMc0Ch0 in new FSP releases. The definition of the upd also changed. Changed FSP meminit code to work based on new definition of the UPDs. Before: 0:Enable both DIMMs, 1:Disable DIMM0, 2:Disable DIMM1, 3:Disable both DIMMs After: 0:Enable, 1:Disable TEST=Boot to OS Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I5af11ae99db3bbe3373a9bd4ce36453b58d62fec Reviewed-on: https://review.coreboot.org/c/coreboot/+/54036 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-16vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2162_00Ronak Kanabar
The headers added are generated as per FSP v2162_00. Previous FSP version was v2117_00. Changes Include: - Adjust UPD Offset in FspmUpd.h and FspsUpd.h - Remove DisableDimmMc*Ch* Upds in FspmUpd.h - Add DisableMc*Ch* Upds in FspmUpd.h - Few UPDs description update in FspmUpd.h and FspsUpd.h Change DisableDimmMc*Ch* to DisableMc*Ch* in meminit.c to avoid compilation failure other change related to UPDs name change will be part of next patch in relation chain. BUG=b:187189546 BRANCH=None TEST=Build and boot ADLRVP using all the patch in relation chain. Change-Id: Ic8d7980146f1bfc96472ef504cf9f16eee63a13e Cq-Depend: chrome-internal:3831865, chrome-internal:3831864, chrome-internal:3831913 Cq-Depend: chromium:TODO Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54083 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-05-14soc/intel/alderlake: Update CPU and IGD Device IDsMaulik V Vaghela
Updated CPU ID and IGD ID for Alder Lake as per EDS. TEST=Code compilation works and coreboot is able to boot and identify new device Ids. Change-Id: I2759a41a0db1eba5d159edfc89460992914fcc3c Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-05-14soc/intel/alderlake: Add known GPIO virtual wire informationDeepti Deshatty
GPIO communities 0, 1, and 4 have virtual wire indexes & bits for at least some of their groups; add the known information into the community definitions. This patch is ported form tigerlake. Change-Id: I2f1e2413d06e8afe4233d7111763cb45b78f845b Signed-off-by: Deepti Deshatty <deepti.deshatty@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/54088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 07:57:20 +0000