soc/intel/alderlake: Rename FSP_S_CONFIG variable from params to s_cfg

Align FSP-S UPD structure (FSP_S_CONFIG) variable name (s_cfg) as FSP-M
UPD structure variable (m_cfg).

TEST=Able to build and boot ADLRVP to ChromeOS. FSP-S UPD dump shows
no change in UPD values with this CL.

Change-Id: I795f733f5f0cc64d3a556a1cd401323b35ba5a23
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

1 files changed, 87 insertions, 87 deletions

diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index 605677b5c8..33ad78d19d 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -49,22 +49,22 @@ static int get_l1_substate_control(enum L1_substates_control ctl)
 	return ctl - 1;
 }
 
-static void parse_devicetree(FSP_S_CONFIG *params)
+static void parse_devicetree(FSP_S_CONFIG *s_cfg)
 {
 	const struct soc_intel_alderlake_config *config;
 	config = config_of_soc();
 
 	for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++)
-		params->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
+		s_cfg->SerialIoI2cMode[i] = config->SerialIoI2cMode[i];
 
 	for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) {
-		params->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
-		params->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
-		params->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
+		s_cfg->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i];
+		s_cfg->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i];
+		s_cfg->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i];
 	}
 
 	for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++)
-		params->SerialIoUartMode[i] = config->SerialIoUartMode[i];
+		s_cfg->SerialIoUartMode[i] = config->SerialIoUartMode[i];
 }
 
 __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config)
@@ -72,7 +72,7 @@ __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *
 	/* Override settings per board. */
 }
 
-static void soc_silicon_init_params(FSP_S_CONFIG *params,
+static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg,
 		struct soc_intel_alderlake_config *config)
 {
 	int i;
@@ -83,112 +83,112 @@ static void soc_silicon_init_params(FSP_S_CONFIG *params,
 	mainboard_update_soc_chip_config(config);
 
 	/* Parse device tree and enable/disable Serial I/O devices */
-	parse_devicetree(params);
+	parse_devicetree(s_cfg);
 
 	microcode_file = cbfs_map("cpu_microcode_blob.bin", &microcode_len);
 
 	if ((microcode_file != NULL) && (microcode_len != 0)) {
 		/* Update CPU Microcode patch base address/size */
-		params->MicrocodeRegionBase = (uint32_t)microcode_file;
-		params->MicrocodeRegionSize = (uint32_t)microcode_len;
+		s_cfg->MicrocodeRegionBase = (uint32_t)microcode_file;
+		s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len;
 	}
 
 	/* Load VBT before devicetree-specific config. */
-	params->GraphicsConfigPtr = (uintptr_t)vbt_get();
+	s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get();
 
 	/* Check if IGD is present and fill Graphics init param accordingly */
-	params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
-	params->LidStatus = CONFIG(RUN_FSP_GOP);
+	s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
+	s_cfg->LidStatus = CONFIG(RUN_FSP_GOP);
 
 	/* Use coreboot MP PPI services if Kconfig is enabled */
 	if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
-		params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
+		s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
 
 	/* D3Hot and D3Cold for TCSS */
-	params->D3HotEnable = !config->TcssD3HotDisable;
-	params->D3ColdEnable = !config->TcssD3ColdDisable;
+	s_cfg->D3HotEnable = !config->TcssD3HotDisable;
+	s_cfg->D3ColdEnable = !config->TcssD3ColdDisable;
 
-	params->TcssAuxOri = config->TcssAuxOri;
+	s_cfg->TcssAuxOri = config->TcssAuxOri;
 
 	/* Explicitly clear this field to avoid using defaults */
-	memset(params->IomTypeCPortPadCfg, 0, sizeof(params->IomTypeCPortPadCfg));
+	memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg));
 
 	/*
 	 * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will
 	 * evaluate this UPD value and skip sending command. There will be no
 	 * delay for command completion.
 	 */
-	params->ITbtConnectTopologyTimeoutInMs = 0;
+	s_cfg->ITbtConnectTopologyTimeoutInMs = 0;
 
 	/* Chipset Lockdown */
 	if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) {
-		params->PchLockDownGlobalSmi = 0;
-		params->PchLockDownBiosInterface = 0;
-		params->PchUnlockGpioPads = 1;
-		params->RtcMemoryLock = 0;
+		s_cfg->PchLockDownGlobalSmi = 0;
+		s_cfg->PchLockDownBiosInterface = 0;
+		s_cfg->PchUnlockGpioPads = 1;
+		s_cfg->RtcMemoryLock = 0;
 	} else {
-		params->PchLockDownGlobalSmi = 1;
-		params->PchLockDownBiosInterface = 1;
-		params->PchUnlockGpioPads = 0;
-		params->RtcMemoryLock = 1;
+		s_cfg->PchLockDownGlobalSmi = 1;
+		s_cfg->PchLockDownBiosInterface = 1;
+		s_cfg->PchUnlockGpioPads = 0;
+		s_cfg->RtcMemoryLock = 1;
 	}
 
 	/* USB */
 	for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {
-		params->PortUsb20Enable[i] = config->usb2_ports[i].enable;
-		params->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
-		params->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
-		params->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
-		params->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
+		s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable;
+		s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias;
+		s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias;
+		s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable;
+		s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit;
 
 		if (config->usb2_ports[i].enable)
-			params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
+			s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin;
 		else
-			params->Usb2OverCurrentPin[i] = OC_SKIP;
+			s_cfg->Usb2OverCurrentPin[i] = OC_SKIP;
 	}
 
 	for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) {
-		params->PortUsb30Enable[i] = config->usb3_ports[i].enable;
+		s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable;
 		if (config->usb3_ports[i].enable)
-			params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
+			s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin;
 		else
-			params->Usb3OverCurrentPin[i] = OC_SKIP;
+			s_cfg->Usb3OverCurrentPin[i] = OC_SKIP;
 
 		if (config->usb3_ports[i].tx_de_emp) {
-			params->Usb3HsioTxDeEmphEnable[i] = 1;
-			params->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
+			s_cfg->Usb3HsioTxDeEmphEnable[i] = 1;
+			s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp;
 		}
 		if (config->usb3_ports[i].tx_downscale_amp) {
-			params->Usb3HsioTxDownscaleAmpEnable[i] = 1;
-			params->Usb3HsioTxDownscaleAmp[i] =
+			s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1;
+			s_cfg->Usb3HsioTxDownscaleAmp[i] =
 				config->usb3_ports[i].tx_downscale_amp;
 		}
 	}
 
 	for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) {
 		if (config->tcss_ports[i].enable)
-			params->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
+			s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
 	}
 
 	/* Enable xDCI controller if enabled in devicetree and allowed */
 	if (!xdci_can_enable())
 		devfn_disable(pci_root_bus(), PCH_DEVFN_USBOTG);
-	params->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
+	s_cfg->XdciEnable = is_devfn_enabled(PCH_DEVFN_USBOTG);
 
 	/* PCH UART selection for FSP Debug */
-	params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
-	ASSERT(ARRAY_SIZE(params->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
-	params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
+	s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
+	ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE);
+	s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
 
 	/* SATA */
-	params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
-	if (params->SataEnable) {
-		params->SataMode = config->SataMode;
-		params->SataSalpSupport = config->SataSalpSupport;
-		memcpy(params->SataPortsEnable, config->SataPortsEnable,
-			sizeof(params->SataPortsEnable));
-		memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
-			sizeof(params->SataPortsDevSlp));
+	s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
+	if (s_cfg->SataEnable) {
+		s_cfg->SataMode = config->SataMode;
+		s_cfg->SataSalpSupport = config->SataSalpSupport;
+		memcpy(s_cfg->SataPortsEnable, config->SataPortsEnable,
+			sizeof(s_cfg->SataPortsEnable));
+		memcpy(s_cfg->SataPortsDevSlp, config->SataPortsDevSlp,
+			sizeof(s_cfg->SataPortsDevSlp));
 	}
 
 	/*
@@ -197,8 +197,8 @@ static void soc_silicon_init_params(FSP_S_CONFIG *params,
 	 * Boards not needing the optimizers explicitly disables them by setting
 	 * these disable variables to 1 in devicetree overrides.
 	 */
-	params->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
-	params->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
+	s_cfg->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable);
+	s_cfg->SataPwrOptEnable = !(config->SataPwrOptimizeDisable);
 
 	/*
 	 *  Enable DEVSLP Idle Timeout settings DmVal and DitoVal.
@@ -208,64 +208,64 @@ static void soc_silicon_init_params(FSP_S_CONFIG *params,
 	 */
 	for (i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) {
 		if (config->SataPortsEnableDitoConfig[i]) {
-			params->SataPortsDmVal[i] = config->SataPortsDmVal[i];
-			params->SataPortsDitoVal[i] = config->SataPortsDitoVal[i];
+			s_cfg->SataPortsDmVal[i] = config->SataPortsDmVal[i];
+			s_cfg->SataPortsDitoVal[i] = config->SataPortsDitoVal[i];
 		}
 	}
 
 	/* Enable TCPU for processor thermal control */
-	params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF);
+	s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF);
 
 	/* Set TccActivationOffset */
-	params->TccActivationOffset = config->tcc_offset;
+	s_cfg->TccActivationOffset = config->tcc_offset;
 
 	/* LAN */
-	params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
+	s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
 
 	/* CNVi */
-	params->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
-	params->CnviBtCore = config->CnviBtCore;
-	params->CnviBtAudioOffload = config->CnviBtAudioOffload;
+	s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
+	s_cfg->CnviBtCore = config->CnviBtCore;
+	s_cfg->CnviBtAudioOffload = config->CnviBtAudioOffload;
 	/* Assert if CNVi BT is enabled without CNVi being enabled. */
-	assert(params->CnviMode || !params->CnviBtCore);
+	assert(s_cfg->CnviMode || !s_cfg->CnviBtCore);
 	/* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */
-	assert(params->CnviBtCore || !params->CnviBtAudioOffload);
+	assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload);
 
 	/* VMD */
-	params->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD);
+	s_cfg->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD);
 
 	/* THC */
-	params->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE;
-	params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE;
+	s_cfg->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE;
+	s_cfg->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE;
 
 	/* USB4/TBT */
-	for (i = 0; i < ARRAY_SIZE(params->ITbtPcieRootPortEn); i++)
-		params->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i));
+	for (i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++)
+		s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i));
 
 	/* Legacy 8254 timer support */
-	params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
-	params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
+	s_cfg->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
+	s_cfg->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
 
 	/* Enable Hybrid storage auto detection */
-	params->HybridStorageMode = config->HybridStorageMode;
+	s_cfg->HybridStorageMode = config->HybridStorageMode;
 
 	enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table());
 	for (i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) {
 		if (!(enable_mask & BIT(i)))
 			continue;
 		const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i];
-		params->PcieRpL1Substates[i] =
+		s_cfg->PcieRpL1Substates[i] =
 				get_l1_substate_control(rp_cfg->PcieRpL1Substates);
-		params->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
-		params->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
-		params->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG);
-		params->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
+		s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR);
+		s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER);
+		s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG);
+		s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT);
 	}
 
-	params->PmSupport = 1;
-	params->Hwp = 1;
-	params->Cx = 1;
-	params->PsOnEnable = 1;
+	s_cfg->PmSupport = 1;
+	s_cfg->Hwp = 1;
+	s_cfg->Cx = 1;
+	s_cfg->PsOnEnable = 1;
 }
 
 static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
@@ -278,14 +278,14 @@ static void arch_silicon_init_params(FSPS_ARCH_UPD *s_arch_cfg)
 void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 {
 	struct soc_intel_alderlake_config *config;
-	FSP_S_CONFIG *params = &supd->FspsConfig;
+	FSP_S_CONFIG *s_cfg = &supd->FspsConfig;
 	FSPS_ARCH_UPD *s_arch_cfg = &supd->FspsArchUpd;
 
 	config = config_of_soc();
 
 	arch_silicon_init_params(s_arch_cfg);
-	soc_silicon_init_params(params, config);
-	mainboard_silicon_init_params(params);
+	soc_silicon_init_params(s_cfg, config);
+	mainboard_silicon_init_params(s_cfg);
 }
 
 /*
@@ -314,7 +314,7 @@ void platform_fsp_multi_phase_init_cb(uint32_t phase_index)
 }
 
 /* Mainboard GPIO Configuration */
-__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+__weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg)
 {
 	printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
 }