soc/intel/alderlake: Add get_adl_cpu_type function

This function searches the known MCH device IDs for Alder Lake and
returns the appropriate enum value representing ADL-P, ADL-M, ADL-S, or
unknown.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I26354b340e0c5f15ba246c1cb831d7feaf62d2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

2 files changed, 66 insertions, 0 deletions

diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c
index b97521215e..c5dc804c0f 100644
--- a/src/soc/intel/alderlake/cpu.c
+++ b/src/soc/intel/alderlake/cpu.c
@@ -8,6 +8,7 @@
 
 #include <console/console.h>
 #include <device/pci.h>
+#include <device/pci_ids.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mp.h>
 #include <cpu/x86/msr.h>
@@ -131,3 +132,59 @@ void soc_init_cpus(struct bus *cpu_bus)
 	/* Thermal throttle activation offset */
 	configure_tcc_thermal_target();
 }
+
+enum adl_cpu_type get_adl_cpu_type(void)
+{
+	const uint16_t adl_m_mch_ids[] = {
+		PCI_DEVICE_ID_INTEL_ADL_M_ID_1,
+		PCI_DEVICE_ID_INTEL_ADL_M_ID_2,
+	};
+	const uint16_t adl_p_mch_ids[] = {
+		PCI_DEVICE_ID_INTEL_ADL_P_ID_1,
+		PCI_DEVICE_ID_INTEL_ADL_P_ID_3,
+		PCI_DEVICE_ID_INTEL_ADL_P_ID_4,
+		PCI_DEVICE_ID_INTEL_ADL_P_ID_5,
+		PCI_DEVICE_ID_INTEL_ADL_P_ID_6,
+		PCI_DEVICE_ID_INTEL_ADL_P_ID_7,
+		PCI_DEVICE_ID_INTEL_ADL_P_ID_8,
+		PCI_DEVICE_ID_INTEL_ADL_P_ID_9,
+	};
+	const uint16_t adl_s_mch_ids[] = {
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_1,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_2,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_3,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_4,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_5,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_6,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_7,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_8,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_9,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_10,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_11,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_12,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_13,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_14,
+		PCI_DEVICE_ID_INTEL_ADL_S_ID_15,
+	};
+
+	const uint16_t mchid = pci_s_read_config16(PCI_DEV(0, PCI_SLOT(SA_DEVFN_ROOT),
+							   PCI_FUNC(SA_DEVFN_ROOT)),
+						   PCI_DEVICE_ID);
+
+	for (size_t i = 0; i < ARRAY_SIZE(adl_p_mch_ids); i++) {
+		if (adl_p_mch_ids[i] == mchid)
+			return ADL_P;
+	}
+
+	for (size_t i = 0; i < ARRAY_SIZE(adl_m_mch_ids); i++) {
+		if (adl_m_mch_ids[i] == mchid)
+			return ADL_M;
+	}
+
+	for (size_t i = 0; i < ARRAY_SIZE(adl_s_mch_ids); i++) {
+		if (adl_s_mch_ids[i] == mchid)
+			return ADL_S;
+	}
+
+	return ADL_UNKNOWN;
+}
diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h
index 71c2f47605..b25979d261 100644
--- a/src/soc/intel/alderlake/include/soc/cpu.h
+++ b/src/soc/intel/alderlake/include/soc/cpu.h
@@ -19,4 +19,13 @@
 #define C9_POWER	0xc8
 #define C10_POWER	0xc8
 
+enum adl_cpu_type {
+	ADL_UNKNOWN,
+	ADL_M,
+	ADL_P,
+	ADL_S,
+};
+
+enum adl_cpu_type get_adl_cpu_type(void);
+
 #endif