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path: root/src/soc/intel/alderlake
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2023-04-07mb/google/brya: Enable asynchronous End-Of-PostJeremy Compostella
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74215 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-05Revert "mb/google/brya: Enable asynchronous End-Of-Post"Nick Vaccaro
This reverts commit 11f2f88a277124713f7b0023f078fcc2e1a98c32. Revert initial change as it was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74206 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04soc/intel/alderlake: Add support for CSE timestamp data versionsBora Guvendik
CSE performance data timestamps are different for version 1 Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch moves the current ADL/RPL timestamp definitions to a separate header file. It marks current structure as version 1. BUG=b:259366109 TEST=Boot to OS, check ADL/RPL pre-cpu timestamps. Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-03soc/intel/alderlake: Fix RPL-U 15W and RPL-P 28W TDC current valuesJeremy Compostella
The Intel Power and Performance (PnP) team requested to update the following: - TDC settings for RPL-U 15W variant should be 22A. - TDC settings for RPL-P 28W variant should be 33A. BUG=b:275694022 BRANCH=firmware-brya-14505.B TEST=PnP validated performance impact with these settings on both RPL-U 15W and RPL-P 28W Change-Id: I1141414785a990b975e32ebc03e490b83082aab7 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74046 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02soc/intel/alderlake: Add ADL-P 4+4 with 28W TDPPatrick Rudolph
Add the 28W TDP version of the ADL-P with MCHID 0x4629. Verified that all 28W SoCs have the same PL1/PL2 defined in Intel document #655258 "12th Generation Intel Core Processors Datasheet, Volume 1 of 2". Fixes the error seen in coreboot log: [ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-03-31mb/google/brya: Enable asynchronous End-Of-PostJeremy Compostella
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-31soc/intel/alderlake: Enable 'struct cpu_info' update for ADLSridhar Siricilla
The patch enables addition of core_type member to 'struct cpu_info' for Alderlake platform. TEST=Build and verify the code for Gimble Change-Id: Ia065b98c2013e78328fd38bed9c667792d6d1f4d Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74089 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-30soc/intel/alderlake: Avoid reprogramming the SRAM BARSubrata Banik
This patch avoids the redundant programming of SRAM BAR when the SRAM PCI device is enabled. Rather read the PCH SRAM Base Address Register while enabling crashlog feature. Additionally, this patch relies on PCI enumeration to get the SRAM BAR rather than hijacking the SPI temporary base address which might have resulted in problems if SPI is disabled on some platform with BAR being implemented. TEST=Able to build and boot google/marasov and crashlog is working. Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-26soc/intel: Move USB PORTSC definition into IA common codeSubrata Banik
This patch moves USB Port Status and Control (PORTSC) Reg definition into IA common code to allow other SoC code to reuse it without redefining the same for each SoC. TEST=Able to build and boot google/taeko where USB wake is working. Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-21soc/intel/alderlake/vr_config: Add i3-1220PEPatrick Rudolph
Add the AlderLake-P 4+4+2 (28W) with MCH_ID 0x4629 to the vr_config table. Change-Id: I606ef429f47dfe386177f7257b153acc1611bb61 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-03-17soc/intel/alderlake: Hook the VT-d DMA protection optionMichał Żygowski
TEST=Enable DMA protection on MSI PRO Z690-A DDR4 and observe the I/O devices like USB and NVMe fail to enumerate in UEFI Payload (basically proving that DMA protection works). Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Iecaa3d04f1447b7e73507ca57a0d23d42e24d663 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68450 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake/hsphy.c: Handle case with DMA protectionMichał Żygowski
The HSPHY firmware must be downloaded to DMA-allowed host address space. Check for DMA buffer presence and use it as the buffer for HSPHY firmware to be downloaded from CSME. TEST=Successfully load HSPHY firmware to CPU on MSI PRO Z690-A DDR4 with DMA protection enabled. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I88edda26a027b557eeaba80426a5b7be7199507d Reviewed-on: https://review.coreboot.org/c/coreboot/+/68556 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-17soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_VTDMichał Żygowski
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I226305fa547e9d9ea541a5806d543aa358bce28d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72069 Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15soc/intel/alderlake: Select `X86_CLFLUSH_CAR` configLean Sheng Tan
This patch selects `X86_CLFLUSH_CAR` config for running `clflush` to invalidate the cache region based on commit 3134a81 for boot performance improvement. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I1fe6072a3c23a02c9a691406f179bfc8f0f18a93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-09soc/intel: Update API name `pmc_send_bios_reset_pci_enum_done`Subrata Banik
This patch updates PMC API name from `pmc_send_pci_enum_done` to `pmc_send_bios_reset_pci_enum_done` to inform PMC IPC about BIOS done is also set along with PMC enumeration being done. BUG=b:270942083 TEST=Able to build and boot google/rex. Change-Id: I1cf8cb1ecadeb68c109be6b0e751a3f2c448ae4f Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-07soc/intel/adl: Increase MAX_CPUS to 32 for RPLTim Crawford
Raptor Lake i9 CPUs have 8P+16E cores for a total of 32 threads. Change-Id: I26a729a585e7dc14f38c9092056eb0280726f053 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73514 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-05soc/intel/alderlake: Hook up ucode for RPL-P/H/UTim Crawford
Hook up microcode from 3rdparty repo for: - 06-ba-02 (CPUID signature: 0xb06a2) Change-Id: Icb2fc9350ebc33ef150f1ab5df1006ed956478d6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73436 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-04soc/intel/alderlake: Allow channel 0 for memory-downTim Crawford
Fixes detection of the on-board RAM (Samsung K4AAG165WA-BCWE) on the System76 Lemur Pro 11 (lemp11). Change-Id: Ibe56c0f2b81d660303429cd2e21a7bb6cd433da5 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04soc/intel/alderlake: Add UWES ASL into xhci.aslScott Chao
Align support for enable wake-on-usb attach/detach as was introduced in Cannon Lake in commit 811284125f0a ("soc/intel/cannonlake: Add UWES ASL into xhci.asl"). This adds the USB Wake Enable Setup (UWES) ASL blocks required to inform the OS about plug wake events bits being set in the PORTSCN register configured by devicetree. BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <Scott_Chao@wistron.com> Change-Id: Icbc427a89413f5fe3a4a533135cc2c39349a9580 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-02soc/intel/alderlake: Hook up ucode for RPL-S/HX B0Tim Crawford
Hook up microcode from 3rdparty repo for: - 06-b7-01 (CPUID signature: 0xb0671) Verified microcode blob was in CBFS on Clevo PD50SNE (system76/serw13), which has an i9-13900HX. Change-Id: If91ff9233a5e1dd1db76edf33a76c55f5dddc9b4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-01soc/intel/alderlake: Hook up PchHdaAudioLinkHdaEnable to devicetreeSean Rhodes
The comment that the PchHdaAudioLink UPDs only configure GPIOs is incorrect. Setting this GPIO to 1 or 0 will not change the HDA GPIO configuration; it will make the sound work when set to 1, or not work when set to 0. Remove the incorrect comment and make the UPD configurable from the devicetree. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6f27f41a4a4b3844a65d45d36aba37c3af1050a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71715 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-03-01soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbolSean Rhodes
Replace the SOC_INTEL_TIGERLAKE_S3 and SOC_INTEL_ALDERLAKE_S3 with the D3COLD_SUPPORT symbol, as it allows for more granular control. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07e8c84e5ad8f390bfbac017dd23736e7a6ced9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-25soc/intel/{adl, cmn, mtl}: Refactor MP Init related configsSubrata Banik
This patch optimizes CPU MP Init related configs being used within multiple SoC directory and moving essential configs into common code to let the SoC user to choose as per the requirement. TEST=Able to build and boot google/kano and google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I12adcc04e84244656a0d2dcf97607bd036320887 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73196 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-24soc/intel/adl: Select CSE defined ME spec version for alderlakeDinesh Gehlot
Alderlake based SoCs uses Intel's Management Engine (ME), version 16. This patch selects ME 16 specification defined at common code and removes alderlake SoC specific ME code and data structures. BUG=b:260309647 Test=Build verified for brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ib94e4662c735b1c31c8dfca1cfa881e6fa4070fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/73244 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-23intel/alderlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for RPL & ADL-N based ChromeOS platforms. It is not disabled for ADL-P based platforms because ADL-P FSP relies on MBP HOB for ChipsetInit version for ChipsetInit sync. As ChipsetInit sync doesn't occur if no MBP HOB, so it results S0ix issue. This limitation is addressed in the later platforms so creation of MBP HOB can be skipped for ADL-N and RPL based platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Taniks. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ia396b633a71aedf592c45b69063ee0528840fd2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-23Revert "soc/intel/adl: Select CSE defined ME spec version for alderlake"Lean Sheng Tan
This reverts commit 272c9c07bd9c7dcd684614c67487504ce06f7a36. Reason for revert: Sorry was going to give +2 but pressed the submit button and accidentally merged this out of train. Change-Id: I8a2c6407832bdcf3d475209356501f8fc3672f6b Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73213 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-23soc/intel/adl: Select CSE defined ME spec version for alderlakeDinesh Gehlot
Alderlake based SoCs uses Intel's Management Engine (ME), version 16. This patch selects ME 16 specification defined at common code and removes alderlake SoC specific ME code and data structures. BUG=b:260309647 Test=Build verified for brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I94cb8a9cbb6167d1a11a012efbd6a135a8692969 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73135 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-23soc/intel: Use common codeflow for MP initArthur Heymans
This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*: Remove lapic from devicetree). Alderlake cpu code was linked in romstage but unused so drop it. Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72604 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-20soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORTSean Rhodes
Select NO_S0IX_SUPPORT for `starlabs/starbook` and `atlas/prodrive` so their configurations are unchanged. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I718952165daa6471f11e8025e745fe7c249d3b46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72800 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-15soc/intel/alderlake: Disable package C-state demotion for Raptor LakeAnil Kumar
While executing S0ix tests on Raptor Lake boards, we observed CPU fails to enter suspend state, causing failure. As a workaround, disable package C-state demotion, till this issue is fixed in ucode. BUG=268296760 BRANCH=firmware-brya-14505.B TEST=Boot and verified that S0ix issue is resolved. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ie50e1024f4118d82d2ad762b54fa722c43990d12 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72942 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-15soc/intel/adl: Correct wrongly reported ADL PCH SKULean Sheng Tan
Per Intel 600 & 700 series PCH EDS (626817), these PCH IDs belongs to ADL not RPL, though some RPL SoCs are also using ADL PCH. Hence correct the name reporting to avoid confusion when ADL SoCs were used. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I61a608e2c99b1d60a99d6ad734b396676f3a2ab2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72999 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-14soc/intel/alderlake: Add missing SATA DSDT devicePatrick Rudolph
Add "SATA" to DSDT as it's referenced by Intel PEP SSDT. Fixes warning shown in Linux: ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_SB_.PCI0.SATA (20220331/dspkginit-438) Change-Id: I65a1d17bce246022859f011cdc4712e1206a98fe Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72762 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-02-13soc/intel/alderlake: Fix ACPI name for DPTFCoolStar
The correct ACPI device for DPTM is TCPU; fixing this puts the participant devices under the correct parent device, and allows Windows to properly go into S0ix. TEST=builb/boot Win11 on google/banshee, verify Si0x functional. Change-Id: I1b3e2655d4d42e008dead9bc87b73ce02868fdfa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-02-09Revert "device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORT"Felix Singer
This reverts commit d6e04aa00bc5a8912a041a569eb57f6962d1119a. Reason for revert: Breaks master. Change-Id: If7daeaaffe3f9ae9f5e2fbecef5817b9b62827d3 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72917 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-02-08device: Add Kconfig options for D3COLD_SUPPORT and NO_S0IX_SUPPORTSean Rhodes
Add NO_S0IX_SUPPORT for boards that do not support, or do not want to support S0IX. As all the boards in the tree that do this, don't support D3Cold, add D3COLD_SUPPORT that defaults to `n` when NO_S0IX_SUPPORT is selected to disable D3Cold support. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I04abc7efe2db06ae6daba9e09835441b62ee44f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-02-08soc/intel/{tgl,adl}/acpi: Unify the way D3Cold is enabledSean Rhodes
Both Alder Lake and Tiger Lake have Kconfig options for S3, which disables support for D3Cold. Unify these so that they are easier to compare. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6eaba99e5483053a91ca20df2b7788edac5d65b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72798 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07soc/intel/alderlake: Remove unused S0IX variableSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I85fc5dabf10c6df7f11fd1defe8a39afc9f95325 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72797 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev treeKane Chen
This commit provides a dev tree setting for partners to enable/disable TccoldHandshake for the sighting in doc:723158 BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=compile ok and FSP UPD is config properly Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68635 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03soc/intel/alderlake: Add a few missing definitions in iomap.hJeremy Compostella
Some reserved address range listed in Alder Lake Platform Firmware Architecture Specification document 626540 section 6.4 ADL - System Memory Map such as North TraceHub ranges were missing. Details about North TraceHub (aka. Intel TraceHub) can be found in Intel Trace Hub (Intel TH) Developer's Manual document 671536. BUG=b:264648959 TEST=Compilation successful Change-Id: I14803a7297c8c5edefe564d92bfe7314f6769942 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-03soc/intel/alderlake: Add a missing RPL-P power limits configurationJeremy Compostella
This patch adds the {MCH:a706, TDP:28W} missing 28W configuration. BUG=b:267666609 BRANCH=firmware-brya-14505.B TEST=Power Limit are properly set on skolas 28W Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-02soc/intel/alderlake: Add entries to eventLog on invocation of early SOLTarun Tuli
If we show the user early signs of life during CSE FW sync or MRC (re)training, log these to the eventLog (ELOG_TYPE_FW_EARLY_SOL). These can be used to ensure persistence across global reset (e.g. after CSE sync) so that they can be later retrieved in order to build things such as test automation ensuring that we went through the SOL path/display initialized. BUG=b:264648959 TEST=event shows in eventlog after CSE sync and/or MRC Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2 Signed-off-by: Tarun Tuli <taruntuli@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71295 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-02-01treewide: Remove duplicated include <device/pci.h>Elyes Haouas
<device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31soc/intel/alderlake: Pick an unused and safer graphics address spaceJeremy Compostella
It turns out that the [0xfa000000-0xfaffffff] range conflicts with some North TraceHub address space ranges ([0xfad00000-0xfadfffff] and [0xfacfc000-0xfacfffff]). Experiments have established that this conflicting range results in an unpected PIPE A underrun issue reported by i915 and some visible flickers on the display during boot. The [0xf0000000-0xffffffff] range is a crowded memory space with resources statically assigned to some devices but also some ranges used at various point in the boot flow by the FSP. To not run into any other potential conflicts, we want to pick a unused memory space. But at this early stage of the boot, we do not have full knowledge of what memory space is going to be used by the FSP. As a result, we decided to pick the [0xaf000000-0xafffffff] range as: 1. It does not conflicting with any coreboot memory space usage 2. It is the address the FSP uses by default for GFX MMIO BAR0 and as such should not conflict with any FSP memory space usage. BUG=b:264648959 BRANCH=firmware-brya-14505.B TEST=No flickers observed on boot Change-Id: I6a00350ff4007bb7692d2ff6598b946cc6123302 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72605 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-27soc/intel/adl: remove DPTF from D-states list used to enter LPMEran Mitrani
The D-state list lists the devices with the corresponding D-state that the devices should be in, in order to enter LPM DPTF is not mentioned in Intel's document 595644 as one of the devices. This CL removes it to avoid an error seen after it was added to that table: "ACPI Error: AE_NOT_FOUND, While resolving a named reference package element - \_SB_.PCI0.DPTF (20200925/dspkginit-438)" TEST=Built and tested on anahera and saw the error is gone BUG=b:231582182 Change-Id: I00eddd7e4cc71a0c25e77ff53025dee5bf942de1 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72199 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-01-26soc/intel/alderlake: Wait for panel power cycle to completeJeremy Compostella
The Alder Lake PEIM graphics driver executed as part of the FSP does not wait for the panel power cycle to complete before it initializes communication with the display. It can result in AUX channel communication time out and PEIM graphics driver failing to bring up graphics. If we have performed some graphics operation in romstage, it is possible that a panel power cycle is still in progress. To prevent any issue with the PEIM graphics driver it is preferable to ensure that panel power cycle is complete. This patch replaces commit ba2cef5b5493 ("soc/intel/common/block/early_graphics: Introduce a 200 ms delay") workaround patch. BUG=b:264526798 BRANCH=firmware-brya-14505.B TEST=Developer screen is visible in the recovery flow Change-Id: Iadd6c9552b184f7d6ec8df9d0d392634864ba50b Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72419 Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-25soc/intel/alderlake: Increase premem cbmem buffer size to 16KBTarun Tuli
Current size of the cbmem premem buffer (8KB) is sometimes insufficient to contain the complete debug log causing the cbmem console buffer to indicate overflow. This patch increases the premem cbmem buffer size to 16KB so that the complete debug log can be stored in it. TEST=Make sure that logs from all the boot stages can be seen using 'cbmem -c'. Change-Id: I60c68322c52191eabf7e06b4be06e66f90ff8751 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71290 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-24soc/intel/alderlake: Increase cbmem buffer size for the debug imageTarun Tuli
Currently most of the FSP debug messages (when enabled) are truncated due to insufficient size of cbmem buffer. Increase premem cbmem console size to 0x16000 bytes and cbmem buffer size to 0x100000 bytes so that cbmem buffer can contain most of the debug logs when FSP debug messages are enabled. TEST=Verify output of 'cbmem -c' when FSP debug messages are enabled but MRC debug message. Change-Id: I0273fb14916f213b686270a9dec4c1b47612af4d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71289 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-24soc/intel/alderlake: Increase cbmem buffer size to 256KBTarun Tuli
Current size of the cbmem buffer (128KB) is insufficient to contain the complete debug log causing the cbmem console buffer to wrap. This patch increases cbmem buffer size to 256KB so that the complete debug log can be stored in it. TEST=Make sure that logs from all the boot stages can be seen using 'cbmem -c'. Change-Id: I2099386dd87a010c3a5937bd896620270f587b1c Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71288 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-24soc/intel/alderlake: Implement API to disable UFS controllersSubrata Banik
This patch implements a new API to make the UFS controller function disabled. Additionally, perform a warm reset post disabling the UFS controller to let PMC know about the state of the UFS controller and disable the MPHY clock. BUG=b:264838335 TEST=Able to build and boot Google/Marasov successfully. From the AP log, I am able to confirm that UFS is function disabled using PSF. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I940a634f70f8c97ef1234866d4c5a1ff224c6e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71989 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-24soc/intel/adl: Option to create unified AP FW for UFS/Non-UFS SKUsSubrata Banik
This patch makes it easy for OEMs to keep a unified AP firmware image to boot different SKUs with UFS and non-UFS as boot media. With a unified image while booting on non-UFS SKU is exhibiting S0ix failure due to UFS remain enabled in the strap although FSP-S is making the UFS controller function disabled. The potential root cause of this behaviour is although the UFS controller is function disabled but MPHY clock is still in active state. A possible solution to this problem is to issue a warm reboot (if boot path is S5->S0 or G3->S0) after disabling the UFS and let PMC read the function disable state of the UFS for disabling the MPHY clock. Mainboard users with such board design where OEM would like to use an unified AP firmware to support both UFS and non-UFS sku booting might need to choose this config to allow disabling UFS while booting on the non-UFS SKU. Note: selection of this config would introduce an additional warm reset in cold-reset scenarios due to function disabling of the UFS controller. BUG=b:264838335 TEST=Able to build and boot Google/Marasov successfully. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I0a811d8f4aad41dab6f8988329eaa1d590a4637a Reviewed-on: https://review.coreboot.org/c/coreboot/+/71988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-24soc/intel/alderlake: Inform user during CSE updateJeremy Compostella
If a CSE update is going to happen and early graphics is supported by the mainboard, an on-screen text message is displayed to inform the end user. CSE update can take a while and an impatient end user facing a black screen for a while may reset the device unnecessarily. BUG=b:264648959 BRANCH=firmware-brya-14505.B TEST=On screen text message during CSE update observed on skolas Change-Id: I28c4fef9345d577be287b76a2a767b5c852ec742 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72098 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-22soc/intel/{adl,mtl,tgl}: change selection for ↵Matt DeVillier
DEFAULT_SOFTWARE_CONNECTION_MANAGER Needs to be selected for ChromeOS mainboards even for non-ChromeOS builds, else Thunderbolt/USB4 doesn't work under Windows (and likely Linux as well). TEST=build/boot Windows on drobit/banshee, verify TB functional Change-Id: Iee3f99840f0c6cc384d9fdef6dff55bcbfc0380f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72140 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20soc/intel: Remove unused <stddef.h>Elyes Haouas
Change-Id: I8432d799c9bf23058b7b903bb07f6c2b4308eeba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72103 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18soc/intel/alderlake: Add print that MRC training screen displayedTarun Tuli
Add a INFO print indicating that we did infact attempt to display the MRC training message to the user. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Print seen in cbmem -c Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I1a20fb221aa2fa0eeaf9b7f8cf3d8a8ab0b91133 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-01-18soc/intel/alderlake: Fix incorrect `prev_sleep_state` issueSubrata Banik
The patch fixes indication of incorrect `prev_sleep_state` on the next boot after global reset trigger. The existing code misses an important check about `if PCH doesn't set the WAK_STS` while checking power failure. As a result, every early warm/global reset is considered as power failure after looking into the PMC MMIO CON-A register alone (as ignoring the ACPI PM_CTRL.WAK_STS bit). As per the code comment this code logic is expected to check the power failure reason if PCH doesn't set the WAK_STS while waking from G3 state. TEST=Able to build and boot google/taeko. Without this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 5` although the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 5 With this patch: Observation: Resuming after a warm reset is considered as `prev_sleep_state 0`. It matches with the SLP_TYP is zero and WAK_STS bit is set. pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00000000 GEN_PMCON: d1215238 00002200 .... prev_sleep_state 0 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I52f9c261f4eea34e6d2300c8de97ee018d886189 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71987 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17soc/intel/alderlake: Avoid redundant chipset programming in romstageSubrata Banik
This patch refactors the mainboard_romstage_entry() function to avoid redundant chipset programming caused by global reset due to CSE FW sync operation. Hence, keeping only the minimal and mandatory operations required to perform CSE FW sync successfully. This would help to optimize the boot flow by removing redundant programming like SA, SMBUS twice in every CSE FW update path. TEST=Able to build and boot Google/Marasov successfully. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Iba9767ef51d7fc7ecf9de14454105865433ba041 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71932 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/alderlake: Inform user of memory trainingJeremy Compostella
If memory training is going to happen and early graphics is supported by the mainboard, an on-screen text message is displayed to inform the end user. Memory training can take a while and an impatient end user facing a black screen for a while may reset the device unnecessarily. BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=On screen text message during MRC training observed on skolas Change-Id: I4ea15123eed1a4355c5ff7d815925032d4151de0 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70300 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-12soc/intel/alderlake: Add romstage early graphics supportJeremy Compostella
BUG=b:252792591 BRANCH=firmware-brya-14505.B TEST=Verify that VGA text mode is functional in romstage Change-Id: I727b28bbe180edc2574e09bf03f1534d6282bdb2 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70303 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11soc/intel/alderlake: Move ME firmware status register structures toDinesh Gehlot
pertinent header file This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarilly share the same SoC directory. BUG=b:260309647 Test=Able to build and boot Google/brya. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: Ic14305b0479a8c57531d9930946eded7ac518b09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71625 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-11device/Kconfig: Fix selection of software connection managerMartin Roth
The patch that introduced the selection of software connection manager, CB:64561 - 060df17f1d (soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCM) added a default to enable the software configuration manager directly in the choice. This leads to warnings when running make menuconfig: src/soc/intel/alderlake/Kconfig:439: warning: defaults for choice values not supported src/soc/intel/meteorlake/Kconfig:337: warning: defaults for choice values not supported src/soc/intel/tigerlake/Kconfig:299: warning: defaults for choice values not supported I'm not sure why the Kconfig linter didn't catch this, but this issue is currently breaking the build for me. This patch fixes it so that instead of setting the default directly, a new Kconfig value is selected that then sets the default correctly. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I674046a93af8f7c2f3003900804deefa89dae295 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71776 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-11soc/intel/{alderlake,tigerlake}: Fix typo in gpio_defs.hJakub Czapiga
Alder Lake and Tiger Lake had unnecessary lower-case 'i' in GPP_C0_IRQ define name. Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ida892b00e5a28544950cb9863d0ff2408a514576 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71819 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-01-10soc/intel: Add Kconfigs to define scaling factor for coresSridhar Siricilla
The patch adds Kconfigs to define scaling factor for Efficient and Performance cores instead of using hard coded values in the soc code. Also, the patches uses the Kconfigs directly to calculate the core's nominal performance. So, we don't need to implement soc function soc_get_scaling_factor() to get the scaling factor data for different core types. Hence, soc_get_scaling_factor() function is removed. TEST=Build the code for Gimble and Rex. Also, I have verified that build system logs error when the Kconfigs are undefined. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I55e4d815116ef40c5f33be64ab495e942bf35ee8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71687 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-09soc/intel/alderlake: Disable Intel TXT based on `INTEL_TXT` configSubrata Banik
This patch makes the call into TXT lib in order to disable the TXT if SoC user haven't selected the `INTEL_TXT` config. Disabling TXT would be helpful to access VGA framebuffer prior calling into FSP-M. TEST=Able to perform disable_txt and unlock memory which helped to access VGA framebuffer prior calling into FSP-M. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9dd7c5492a5f45eef0dd9e836cc2da1844c78919 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71575 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-08soc/intel/alderlake/acpi: Add Kconfig options for SCM and FCMSean Rhodes
Software Connection Manager doesn't work with Linux 5.13 or later, resulting in TBT ports timing out. Not advertising this results in Firmware Connection Manager being used and TBT works correctly. Add Kconfig options to chose between SCM (Software Connection Manager) and FCM (Firmware Connection Manager). FCM is primary, as it's more compatible save for ChromeOS devices as ChromeOS uses SCM. Linux patch: torvalds/linux@c6da62a c6da62a219d028de10f2e22e93a34c7ee2b88d03 Tested with StarBook Mk VI (i7-1260P). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Iac31d37c0873f41f7b14e1051fe214466d1ebdd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64561 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-06soc/intel/: Rename small and big cores referencesSridhar Siricilla
The patch addresses Intel heterogeneous cores as `Efficient` and `Performance` cores instead of `small` and `big` cores. It is to ensure coreboot code has uniform reference to the heterogeneous cores. So, the patch renames all `small` and `big` core references to `efficient` (eff) and `performance` (perf) cores respectively. TEST=Build the code for Brya and Rex boards Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I98c9c0ed86b211d736a0a1738b47410faa13a39f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71639 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-01-04soc/intel: Create common function to check PCH slotKapil Porwal
BUG=none TEST=Build and boot to google/taniks. Check dmesg and make sure that there is no regression. Also confirm that there is no change in ACPI _PRT and IO-APCI interrupt assignment. IO-APIC interrupts before and after this patch: 1: IO-APIC 1-edge i8042 8: IO-APIC 8-edge rtc0 9: IO-APIC 9-fasteoi acpi 14: IO-APIC 14-fasteoi INTC1055:00 23: IO-APIC 23-fasteoi idma64.5, ttyS0 37: IO-APIC 37-fasteoi idma64.0, i2c_designware.0 38: IO-APIC 38-fasteoi idma64.1, i2c_designware.1 40: IO-APIC 40-fasteoi idma64.2, i2c_designware.2 41: IO-APIC 41-fasteoi idma64.3, i2c_designware.3 42: IO-APIC 42-fasteoi idma64.4, i2c_designware.4 45: IO-APIC 45-fasteoi idma64.6, pxa2xx-spi.6 77: IO-APIC 77-edge cr50_i2c 100: IO-APIC 100-fasteoi ELAN0000:00 103: IO-APIC 103-fasteoi chromeos-ec _PRT before and after this patch: Package (0x04) ==> 0x0001FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0002FFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x0004FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0005FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x0006FFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x0007FFFF, 0x00, 0x00, 0x00000013 Package (0x04) ==> 0x0007FFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x0007FFFF, 0x02, 0x00, 0x00000015 Package (0x04) ==> 0x0007FFFF, 0x03, 0x00, 0x00000016 Package (0x04) ==> 0x0008FFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x000DFFFF, 0x00, 0x00, 0x00000011 Package (0x04) ==> 0x000DFFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0010FFFF, 0x00, 0x00, 0x00000018 Package (0x04) ==> 0x0010FFFF, 0x01, 0x00, 0x00000019 Package (0x04) ==> 0x0010FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0010FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0011FFFF, 0x00, 0x00, 0x0000001A Package (0x04) ==> 0x0011FFFF, 0x01, 0x00, 0x0000001B Package (0x04) ==> 0x0011FFFF, 0x02, 0x00, 0x0000001C Package (0x04) ==> 0x0011FFFF, 0x03, 0x00, 0x0000001D Package (0x04) ==> 0x0012FFFF, 0x00, 0x00, 0x0000001E Package (0x04) ==> 0x0012FFFF, 0x01, 0x00, 0x0000001F Package (0x04) ==> 0x0012FFFF, 0x02, 0x00, 0x00000016 Package (0x04) ==> 0x0013FFFF, 0x00, 0x00, 0x00000020 Package (0x04) ==> 0x0013FFFF, 0x01, 0x00, 0x00000021 Package (0x04) ==> 0x0013FFFF, 0x02, 0x00, 0x00000022 Package (0x04) ==> 0x0013FFFF, 0x03, 0x00, 0x00000023 Package (0x04) ==> 0x0014FFFF, 0x01, 0x00, 0x00000017 Package (0x04) ==> 0x0014FFFF, 0x00, 0x00, 0x00000024 Package (0x04) ==> 0x0014FFFF, 0x02, 0x00, 0x00000011 Package (0x04) ==> 0x0015FFFF, 0x00, 0x00, 0x00000025 Package (0x04) ==> 0x0015FFFF, 0x01, 0x00, 0x00000026 Package (0x04) ==> 0x0015FFFF, 0x02, 0x00, 0x00000027 Package (0x04) ==> 0x0015FFFF, 0x03, 0x00, 0x00000028 Package (0x04) ==> 0x0016FFFF, 0x00, 0x00, 0x00000012 Package (0x04) ==> 0x0016FFFF, 0x01, 0x00, 0x00000013 Package (0x04) ==> 0x0016FFFF, 0x02, 0x00, 0x00000014 Package (0x04) ==> 0x0016FFFF, 0x03, 0x00, 0x00000015 Package (0x04) ==> 0x0017FFFF, 0x00, 0x00, 0x00000016 Package (0x04) ==> 0x0019FFFF, 0x00, 0x00, 0x00000029 Package (0x04) ==> 0x0019FFFF, 0x01, 0x00, 0x0000002A Package (0x04) ==> 0x0019FFFF, 0x02, 0x00, 0x0000002B Package (0x04) ==> 0x001CFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001CFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001CFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001CFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001DFFFF, 0x00, 0x00, 0x00000010 Package (0x04) ==> 0x001DFFFF, 0x01, 0x00, 0x00000011 Package (0x04) ==> 0x001DFFFF, 0x02, 0x00, 0x00000012 Package (0x04) ==> 0x001DFFFF, 0x03, 0x00, 0x00000013 Package (0x04) ==> 0x001EFFFF, 0x00, 0x00, 0x00000017 Package (0x04) ==> 0x001EFFFF, 0x01, 0x00, 0x00000014 Package (0x04) ==> 0x001EFFFF, 0x02, 0x00, 0x0000002C Package (0x04) ==> 0x001EFFFF, 0x03, 0x00, 0x0000002D Package (0x04) ==> 0x001FFFFF, 0x01, 0x00, 0x00000016 Package (0x04) ==> 0x001FFFFF, 0x02, 0x00, 0x00000017 Package (0x04) ==> 0x001FFFFF, 0x03, 0x00, 0x00000014 Package (0x04) ==> 0x001FFFFF, 0x00, 0x00, 0x00000015 Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Ib4fc850228b7ddbf84e2feb2433adff5e4002033 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71236 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27soc/intel/alderlake: Use common gpio.h includeDinesh Gehlot
Replace the intelblocks/gpio.h and soc/gpio.h includes with the common gpio.h which will include soc/gpio.h which will include intelblocks/gpio.h BUG=b:261778357 TEST=Able to build and boot Google/brya. Change-Id: Ia90a8ea7b4ee125657c7277e3e14018cfe5423a9 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71266 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-27tree/acpi: Replace constant "Zero" with actual numberFelix Singer
Change-Id: I5a3e3506415f424bf0fdd48fc449520a76622af5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71525 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-27{acpi,arch,soc}/acpi: Replace constant "One" with actual numberFelix Singer
Change-Id: I3dfd7dd1de3bd27c35c195bd43c4a5b8c5a2dc53 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71522 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-25soc/intel: Move max speed API to commonDinesh Gehlot
This patch moves API "smbios_cpu_get_max_speed_mhz()" to common code from board specific. This API was made generic in 'commit d34364bdea12 ("soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macro")' BUG=NONE TEST=Boot and verified that SMBIOS max speed value is correct on brya and rex. (brya) dmidecode -t : "Max Speed: 4400 MHz" (rex) dmidecode -t : "Max Speed: 3400 MHz" Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I87040ab23319097287e191d7fc9579f16d716e62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70879 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-24soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATETracy Wu
With enabling FSP Notify Phase APIs, it has chance to issue a global reset in FSP after CSE EOP (with selecting SOC_INTEL_CSE_SEND_EOP_EARLY ), which CSE already in idle mode and cause failure. For this reason we should drop SOC_INTEL_CSE_SEND_EOP_EARLY in all ADL sku and select SOC_INTEL_CSE_SEND_EOP_LATE instead. BUG=b:261544011 BRANCH=firmware-brya-14505.B TEST=tested and verified on Marasov, make sure this kind of global reset can be executed successfully. Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Change-Id: I29736ca8efee64dd03feb48404241ee6295b7c72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-23soc/intel: Drop SoC specific DPTF implementationSubrata Banik
This patch drops the SoC specific implementation as DPTF driver can now fillin those platform specific data using SoC specific macros. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: If65976f15374ba2410b537b1646ce466ba02969b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/alderlake: Add Raptor Lake device IDsMarx Wang
Add system agent ID for RPL QDF#Q2MB/Q2PS TEST=able to build coreboot successfully Signed-off-by: Marx Wang <marx.wang@intel.com> Change-Id: I169c8bc51cdf7fbfcdb1996d93afa4a352e2fddf Reviewed-on: https://review.coreboot.org/c/coreboot/+/71121 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22soc/intel: Set `use_eisa_hids` based on `DPTF_USE_EISA_HID` configSubrata Banik
This patch avoids hardcoding to the `use_eisa_hids` variable instead relying on the SoC config to choose if the SoC platform supports EISA HID. If any SoC platform has the support then the `use_eisa_hids` variable would be set to `true` based on the selection of `DPTF_USE_EISA_HID` config. Note: Prior to Tiger Lake, all DPTF devices used 7-character EISA IDs. If selected, the 7-character _HIDs will be emitted, otherwise, it will use the "new" style, which are regular 8-character _HIDs. Ideally, the platform prior to Tiger Lake would set `use_eisa_hids` to `true` and platform posts that would set `use_eisa_hids` to `false`. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I869bebc8e17c1e65979ca3431308d69771a34fa3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22soc/intel/alderlake: Move DPTF ACPI Device IDs into header fileSubrata Banik
This patch moves DPTF ACPI Device IDs into the header file (soc/dptf.h) so that upcoming patches in this patch train can achieve more common code. TEST=Able to build and boot Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ied32eb301b0702ad7cf12b662886c9060415eb72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71103 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-22drivers/intel/dptf: Add `soc_` prefix for `get_dptf_platform_info()`Subrata Banik
This patch makes the SoC specific callback code more readable by adding `soc_` prefix into the `get_dptf_platform_info()`. In nutshell this patch renames `get_dptf_platform_info()` to `soc_get_dptf_platform_info()`. TEST=Able to build Google/Rex without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27d6a146d5928e1742f82f85f51ad42656f46344 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2022-12-21soc/intel/{adl,mtl,tgl}: Drop unnecessary `dptf.asl`Subrata Banik
This patch drops unused `dptf.asl` from the latest IA SoC platforms as DPTF ACPI code generation is now relies on runtime aka SSDT rather than having fixed dptf.asl files to include inside the mainboard dsdt.asl. TEST=Able to build Google/Kano without any compilation issue. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I30a53eace89bf5324d7c2f15c6c2d2218f90eaf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71087 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-20soc/intel/*/crashlog.[ch]: Remove unused includesElyes Haouas
Change-Id: I126d49c27302e1ed2e00ff491d59cadda7101d12 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70924 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17soc/intel/alderlake: Select SOC_INTEL_CSE_SEND_EOP_LATE for ADL-NReka Norman
On nissa, sending EOP late improves boot time by about 57ms. Before (SOC_INTEL_CSE_SEND_EOP_EARLY): 943:after sending EOP to ME 931,206 (58,431) 943:after sending EOP to ME 932,911 (58,427) 943:after sending EOP to ME 930,908 (58,429) 943:after sending EOP to ME 941,357 (61,748) 943:after sending EOP to ME 933,289 (62,050) 943:after sending EOP to ME 939,578 (62,453) 943:after sending EOP to ME 932,491 (62,050) 943:after sending EOP to ME 929,693 (62,655) 943:after sending EOP to ME 942,247 (62,654) 943:after sending EOP to ME 936,984 (61,751) After (SOC_INTEL_CSE_SEND_EOP_LATE): 943:after sending EOP to ME 1,107,816 (3,498) 943:after sending EOP to ME 1,053,286 (25,212) 943:after sending EOP to ME 1,124,095 (3,511) 943:after sending EOP to ME 1,098,591 (3,498) 943:after sending EOP to ME 1,107,772 (3,499) 943:after sending EOP to ME 1,080,008 (45,969) 943:after sending EOP to ME 1,081,754 (8,024) 943:after sending EOP to ME 1,109,193 (4,102) 943:after sending EOP to ME 1,088,866 (4,201) 943:after sending EOP to ME 1,081,684 (4,203) BUG=b:247902068 TEST=EOP time is improved on nissa (measurements above). Change-Id: I2389831b4ab62f247193b5b0c5ec201e12eaa3db Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70849 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-15soc/intel/{adl, common}: provide a list of D-states to enter LPMEran Mitrani
This was done previously for ADL. moving the code to common so it can be leveraged for other platforms (e.g. MTL) TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15treewide: Remove unused 'include <arch/io.h>'Elyes Haouas
Change-Id: I6f1d7625eb457084ba893b25518fdfdb59cf64db Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70693 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-15soc/intel/{adl, cmn/pcie}: Fix ASPM configuration enum definitionsSubrata Banik
As per PCI Express Base Specification 5.0 section 5.4.1.3 ASPM Configuration +-----------------------+-------------------------------+ | Field Description | ASPM Support | +-----------------------+-------------------------------+ | 00b | No ASPM support | +-----------------------+-------------------------------+ | 01b | L0s Supported | +-----------------------+-------------------------------+ | 10b | L1 Supported | +-----------------------+-------------------------------+ | 11b | L0s and L1 Supported | +-----------------------+-------------------------------+ 100b aka 0x4 is added by FSP to allow auto configuration (to avoid conflicting with the PCI specification defined values). Additionally, changed enum definition which is now meeting the FSP expectations better. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I8c9055f721e144f2ff5055e5f99ea641efc4d268 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70719 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-15soc/intel/alderlake: Disable L1 substates for PCIe compliance test modeBora Guvendik
Disable L1 substates for PCIe compliance test mode in order to get continuous clock output. BUG=b:235863379 TEST=Boot in compliance mode, check FSP settings Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> Change-Id: I2a3b313425e00fe11f616d964f825baaef463c71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70165 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-14soc/intel/alderlake: Utilize `CPU_BCLK_MHZ` over dedicated macroSubrata Banik
This patch drops the redundant macro to define CPU BCLK and instead uses `CPU_BCLK_MHZ` config to calculate the `smbios_cpu_get_max_speed_mhz`. TEST=Able to see max cpu speed is correct in smbios table while trying on Google/Kano. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I5167f3a513c074b9e6986c960e1bcced65f1264c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70676 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-13soc/intel/alderlake/bootblock: Use 'false/true' macrosElyes Haouas
Change-Id: Ic40f1e935b244f39fa3c1322e5128465c57f5e26 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70579 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/intel/alderlake/bootblock: Use read32p()Elyes Haouas
Change-Id: I3062e5b8a0524059b9695dfd32254c5c53598925 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70578 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-12soc/intel/adl/acpi: add entries for HEC1 and SRAM to DSDTAnil Kumar
HEC1 and SRAM are defined in src/soc/intel/alderlake/chipset.cb: device pci 16.0 alias heci1 on end device pci 14.2 alias shared_sram off end This patch adds entries for these devices in DSDT to prevent "AE_NOT_FOUND" errors from kernel TEST=Built and tested on brya to confirm errors are not seen. BUG=b:260258765 Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: Ifd9c509e82ccf02a7801d51513597fe2e5d9e631 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70454 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Cliff Huang <cliff.huang@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-12soc/intel/alderlake/Kconfig: Sort defaults alphabeticallyAngel Pons
"Argh! Lack of consistency! UNACCEPTABLE!" - Emotions Swap the position of two lines so that defaults are listed in alphabetical order according to the PCH type: M, N, P, S. Change-Id: I82a23eb2b5036d3b7ec6766ae9891078f1caab69 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70522 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-10soc/intel: Move TCSS FW latency macros to IA common tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from SoC specific tcss.h to IA common tcss.h Additionally, ensure other structure definitions belonging to the IA common code tcss.h are not causing compilation issues for ASL files (due to including FW latency macros) hence, guarded against `!defined(__ACPI__)`. TEST=Able to build and boot Google/Rex and Google/Kano. Change-Id: Id51545ef714979c6ba09a2b468231b1f4bab0be7 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70487 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10soc/intel/alderlake: Move TCSS FW latency macros to tcss.hSubrata Banik
This patch moves TCSS firmware latency related macros from `tcss_pcierp.asl` to SoC specific `tcss.h`. TEST=Able to build and boot Google/Kano. Change-Id: I96db2dbf050c8f09e4d9c4018a2caa286f7ef1d1 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70485 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-10treewide: Include <device/mmio.h> instead of <arch/mmio.h>Elyes Haouas
<device/mmio.h>` chain-include `<arch/mmio.h>: https://doc.coreboot.org/contributing/coding_style.html#headers-and-includes Also sort includes while on it. Change-Id: Ie62e4295ce735a6ca74fbe2499b41aab2e76d506 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2022-12-07soc/intel: Set IO APIC DMAR entry based on hwArthur Heymans
This avoids the need to hardcode the IOAPIC ID. Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70268 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2022-12-06soc/intel/alderlake: make SOC_INTEL_CSE_SEND_EOP_EARLY per-board configurableMichał Kopeć
SOC_INTEL_CSE_SEND_EOP_EARLY breaks soft ME disable, which works using a HECI message that needs to be sent before EOP. Make the option configurable to allow soft ME disable on alderlake. Change-Id: I7febf7c029e7eac94052cc3a8142949d6813c1bc Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69953 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-02soc/intel/alderlake: Update cpu and pch tracehub modesSridhar Siricilla
The patch gets the cpu and pch's tracehub mode from the debug area of the Descriptor Region and updates the respective UPDs. TEST=Build, verify the tracehub mode values. Update CPU' and PCH's Trace Hub modes: img=coreboot.rom printf '\x01' | dd of=$img bs=1 seek=3841 count=1 conv=notrunc printf '\x01' | dd of=$img bs=1 seek=3842 count=1 conv=notrunc Check coreboot logs: [DEBUG] rt_debug: CPU TraceHub Mode: 1 PCH Tracehub Mode: 1 Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I088b5d1f5569aacbf79834b44372702f8d3a189f Reviewed-on: https://review.coreboot.org/c/coreboot/+/64438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-02soc/intel/alderlake: skip external buses for D-states listEran Mitrani
The devices in the list that was introduced in commit c66ea985776 ("soc/intel/alderlake: provide a list of D-states to enter LPM") are all internal. This CL skips the external buses (which caused the addition of packages to non-existant paths such as "_SB.PCI0.RP1.MCHC", and warnings from the kernel) BUG=b:231582182 TEST=Built and tested on anahera by verifying SSDT contents Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-01soc/intel/alderlake: Drop duplicate macro `PCH_PWRM_BASE_SIZE`Subrata Banik
This patch ensures dropping of the duplicate macro introduced with 'commit 9e4488ab06fd9c4 ("soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS")' `PCH_PWRM_BASE_SIZE` macro represents the size of the PMC MMIO range which can be used as is even in ufs.asl file. BUG=b:252975357 TEST=Build and boot nirwen and see no issues in PLT runs. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70180 Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-11-29soc/intel/alderlake/acpi.c: Don't look up coreboot CPU indexArthur Heymans
The coreboot CPU index for a lapic is arbitrary: it depends on which CPU obtains a spinlock first. Simply using an increasing index will result in consistent ACPI tables across each boot. Change-Id: Iaaaef213b32b33e3ec9f4874d576896c2335211c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69510 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-11-28sb,soc/intel: Address TCO SECOND_TO_STS name collisionKyösti Mälkki
Later soc/intel/common/smbus addresses TCO2_STS as a separate 16-bit register, while baytrail and braswell assumes 32-bit wide TCO1_STS to extend as TCO2_STS. In src/soc/intel/denverton_ns: #define TCO2_STS_SECOND_TO 0x02 In soc/intel/baytrail,braswell: #define SECOND_TO_STS (1 << 17) Elsewehere #define SECOND_TO_STS (1 << 1) It's expected that we remove the first (1 << 17) case and only access TCO2_STS as a separate 16-bit register. For now, use unique names to avoid confusion. Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26src/soc/intel: Remove unnecessary space after castsElyes Haouas
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-11-26soc/intel/alderlake: Use common code CSE-Lite API for WP informationSubrata Banik
This patch drops the local implementation `log_me_ro_write_protection_info` and adopts the API from IA common code (cse_lite.c). BUG=none TEST=Able to compile the cse_lite.c file for google/kano without any error. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69969 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 08:18:35 +0000