diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2022-11-18 15:07:33 +0100 |
|---|---|---|
| committer | Martin L Roth <gaumless@gmail.com> | 2022-11-26 23:39:16 +0000 |
| commit | 9018dee6856791ab599463a771826936c20a80bb (patch) | |
| tree | 079e966e6b894bb9c81ca25e9e783c28947e0e64 /src/soc/intel/alderlake | |
| parent | 5aa98964fb4e2e8c10b1663f8d6a3faa2b700410 (diff) | |
src/soc/intel: Remove unnecessary space after casts
Change-Id: I098104f32dd7c66d7bb79588ef315a242c3889ba
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/alderlake')
| -rw-r--r-- | src/soc/intel/alderlake/bootblock/pch.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/pmutil.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/systemagent.c | 4 |
4 files changed, 5 insertions, 5 deletions
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 712c128d07..83531ded49 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -54,7 +54,7 @@ static void soc_config_pwrmbase(void) pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); /* Enable PWRM in PMC */ - setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); + setbits32((void *)PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); } void bootblock_pch_early_init(void) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 26eba769a1..853b2f2c0d 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -594,7 +594,7 @@ static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, * This would avoid APs from getting hijacked by FSP while coreboot * decides to set SkipMpInit UPD. */ - s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + s_cfg->CpuMpPpi = (uintptr_t)mp_fill_ppi_services_data(); if (CONFIG(USE_FSP_MP_INIT)) /* diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 9389322b31..e6aeed8e7d 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -253,7 +253,7 @@ void soc_fill_power_state(struct chipset_power_state *ps) /* STM Support */ uint16_t get_pmbase(void) { - return (uint16_t) ACPI_BASE_ADDRESS; + return (uint16_t)ACPI_BASE_ADDRESS; } /* diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index 9a8532d6b3..36fa45b9e5 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -84,9 +84,9 @@ int soc_get_uncore_prmmr_base_and_mask(uint64_t *prmrr_base, { msr_t msr; msr = rdmsr(MSR_PRMRR_BASE_0); - *prmrr_base = (uint64_t) msr.hi << 32 | msr.lo; + *prmrr_base = (uint64_t)msr.hi << 32 | msr.lo; msr = rdmsr(MSR_PRMRR_PHYS_MASK); - *prmrr_mask = (uint64_t) msr.hi << 32 | msr.lo; + *prmrr_mask = (uint64_t)msr.hi << 32 | msr.lo; return 0; } |