diff options
author | Tarun Tuli <taruntuli@google.com> | 2023-01-31 18:14:35 +0000 |
---|---|---|
committer | Julius Werner <jwerner@chromium.org> | 2023-02-02 21:44:23 +0000 |
commit | eed31cbc93df2c02d455b91fafcb894a2d467437 (patch) | |
tree | 2187ff7be73171146c6f4d9ea4828f49e3261648 /src/soc/intel/alderlake | |
parent | 5044dc48f34dfd7f0ff08363b2155e27b2f71830 (diff) |
soc/intel/alderlake: Add entries to eventLog on invocation of early SOL
If we show the user early signs of life during CSE FW sync or MRC
(re)training, log these to the eventLog (ELOG_TYPE_FW_EARLY_SOL).
These can be used to ensure persistence across global reset (e.g. after
CSE sync) so that they can be later retrieved in order to build things
such as test automation ensuring that we went through the SOL
path/display initialized.
BUG=b:264648959
TEST=event shows in eventlog after CSE sync and/or MRC
Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2
Signed-off-by: Tarun Tuli <taruntuli@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71295
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/intel/alderlake')
-rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 8 | ||||
-rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 4 | ||||
-rw-r--r-- | src/soc/intel/alderlake/romstage/ux.c | 5 | ||||
-rw-r--r-- | src/soc/intel/alderlake/romstage/ux.h | 2 |
4 files changed, 12 insertions, 7 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 6fec2c7b10..2e8a73cac8 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -6,6 +6,7 @@ #include <cpu/intel/cpu_ids.h> #include <device/device.h> #include <drivers/wifi/generic/wifi.h> +#include <elog.h> #include <fsp/fsp_debug_event.h> #include <fsp/util.h> #include <gpio.h> @@ -423,9 +424,10 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) * training. Memory training can take a while so let's inform the end * user with an on-screen text message. */ - if (!arch_upd->NvsBufferPtr) - ux_inform_user_of_update_operation("memory training"); - + if (!arch_upd->NvsBufferPtr) { + if (ux_inform_user_of_update_operation("memory training")) + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); + } config = config_of_soc(); soc_memory_init_params(m_cfg, config); diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 2ccadbca4a..2c0bdea11a 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -4,6 +4,7 @@ #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> +#include <elog.h> #include <fsp/util.h> #include <intelblocks/cfg.h> #include <intelblocks/cse.h> @@ -149,7 +150,8 @@ static void save_dimm_info(void) void cse_fw_update_misc_oper(void) { - ux_inform_user_of_update_operation("CSE update"); + if (ux_inform_user_of_update_operation("CSE update")) + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); } void cse_board_reset(void) diff --git a/src/soc/intel/alderlake/romstage/ux.c b/src/soc/intel/alderlake/romstage/ux.c index 66b2befee7..5dba194a6b 100644 --- a/src/soc/intel/alderlake/romstage/ux.c +++ b/src/soc/intel/alderlake/romstage/ux.c @@ -6,13 +6,14 @@ #include "ux.h" -void ux_inform_user_of_update_operation(const char *name) +bool ux_inform_user_of_update_operation(const char *name) { if (!CONFIG(MAINBOARD_HAS_EARLY_LIBGFXINIT) || !early_graphics_init()) - return; + return false; printk(BIOS_INFO, "Informing user on-display of %s.\n", name); vga_write_text(VGA_TEXT_CENTER, VGA_TEXT_HORIZONTAL_MIDDLE, "Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device."); + return true; } diff --git a/src/soc/intel/alderlake/romstage/ux.h b/src/soc/intel/alderlake/romstage/ux.h index f09daed93d..e7e1d9957e 100644 --- a/src/soc/intel/alderlake/romstage/ux.h +++ b/src/soc/intel/alderlake/romstage/ux.h @@ -1,3 +1,3 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -void ux_inform_user_of_update_operation(const char *name); +bool ux_inform_user_of_update_operation(const char *name); |