coreboot.git - my copy of coreboot

Age	Commit message (Expand)	Author
2022-04-13	soc/intel/alderlake: Add support for UFS controller	Meera Ravindranath
2022-04-13	soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating	Sridhar Siricilla
2022-04-11	soc/intel/adl: Disable FSP debug output if !FSP_ENABLE_SERIAL_DEBUG	Subrata Banik
2022-04-07	soc/intel/alderlake: Hook up PAVP to Kconfig	Lean Sheng Tan
2022-04-07	soc/intel/alderlake: Hook up VrPowerDeliveryDesign to devicetree	Lean Sheng Tan
2022-03-28	soc/intel/alderlake: Use coreboot native event handler for FSP-M/S	Subrata Banik
2022-03-22	soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config	Kevin Chang
2022-03-17	soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax values	Curtis Chen
2022-03-15	soc/intel/alderlake: Allow mainboard to configure c1-state auto-demotion	MAULIK V VAGHELA
2022-03-15	soc/intel/adl/chip.h: Convert all camel case variables to snake case	MAULIK V VAGHELA
2022-03-07	src: Make PCI ID define names shorter	Felix Singer
2022-02-21	soc/intel/alderlake: Fix function pointer type	Arthur Heymans
2022-02-21	soc/intel/alderlake: Enable eMMC based on dev enabled	Krishna Prasad Bhat
2022-02-04	soc/intel/alderlake: Enable USB2 port reset message on Type-C ports	Anil Kumar
2022-01-26	soc/intel/alderlake: Skip FSP to unlock GPIO Pads	Subrata Banik
2022-01-17	src: Remove unused <cbfs.h>	Elyes HAOUAS
2022-01-13	vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2511_04	Nick Vaccaro
2022-01-07	soc/intel/alderlake: Hook up FSP-S CPU PCIe UPDs	Tim Wawrzynczak
2021-12-03	soc/intel/alderlake: Add TDP to give correct VR configuration	Curtis Chen
2021-11-25	soc/intel/alderlake: Add ADLP 4+4+2 power configurations	Curtis Chen
2021-11-19	soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL-M	Bora Guvendik
2021-11-18	soc/intel/alderlake: Add Acoustic noise mitigation UPDs	Wisley Chen
2021-11-09	soc/intel/alderlake: Enable Intel FIVR RFI settings	Wisley Chen
2021-10-20	soc/intel/alderlake: Fix wrong FIVR configs assignment	Bora Guvendik
2021-10-17	soc/intel: transition full control over PM Timer from FSP to coreboot	Michael Niewöhner
2021-10-15	soc/intel/alderlake: fix NULL pointer dereference	Selma Bensaid
2021-10-06	soc/intel/alderlake: Skip setting D0I3 bit for HECI devices	Subrata Banik
2021-10-04	src/soc/intel/alderlake: Add PsysPmax setting	Ryan Lin
2021-09-29	soc/intel/alderlake: Add ADLP 242 power configurations	Tracy Wu
2021-09-29	soc/intel/alderlake: Add support for power cycle and SLP signal duration	Tim Wawrzynczak
2021-09-25	soc/intel/alderlake: Use intel_microcode_find() to locate ucode.bin	Subrata Banik
2021-09-24	soc/intel/alderlake: Switch to using device pointers	Furquan Shaikh
2021-09-16	drivers/intel/fsp2_0: Refactor MultiPhaseSiInit API calling method	Subrata Banik
2021-09-10	soc/intel/alderlake: Set LpmStateEnableMask UPD	Tim Wawrzynczak
2021-08-26	soc/intel/alderlake: Lock PAM registers in finalize	Tim Wawrzynczak
2021-08-12	soc/intel/alderlake: Clean up FSP chipset lockdown configuration	Felix Singer
2021-08-12	soc/intel/alderlake: Configure the SKU specific parameters for VR domains	V Sowmya
2021-08-12	soc/intel/alderlake: Update the VccIn Aux Imon IccMax for ADL	V Sowmya
2021-08-03	soc/intel/*: Allow configuring 8254 timer via CMOS	Sean Rhodes
2021-07-17	soc/intel/alderlake: Make use of `cpu/intel/cpu_ids.h'	Subrata Banik
2021-07-13	soc/intel/alderlake: Add (and fix) devices in IRQ table	Tim Wawrzynczak
2021-07-12	soc/intel/alderlake: Set max Pkg C-states to Auto	V Sowmya
2021-07-05	soc/intel/alderlake: Add support to update the FIVR configs	V Sowmya
2021-07-02	soc/intel/alderlake: Add USB TCSS enablement	Bernardo Perez Priego
2021-07-01	soc/intel/alderlake: Enable energy efficiency turbo mode	V Sowmya
2021-07-01	soc/intel: Refactor `xdci_can_enable()` function	Angel Pons
2021-06-30	soc/intel/alderlake: Send End-of-Post message to CSE	Tim Wawrzynczak
2021-06-29	soc/intel/alderlake: Enable support for common IRQ block	Tim Wawrzynczak
2021-06-25	soc/intel/alderlake: Fix the typo for FSP_S_CONFIG param	V Sowmya
2021-06-24	soc/intel/alderlake: Refactor soc_silicon_init_params function	Subrata Banik
2021-06-24	soc/intel/alderlake: Rename FSP_S_CONFIG variable from params to s_cfg	Subrata Banik
2021-06-24	soc/intel/alderlake: Refactor platform_fsp_silicon_init_params_cb function	Subrata Banik
2021-06-23	soc/intel/alderlake: Use devfn_disable() function for XDCI	Subrata Banik
2021-06-18	soc/intel/alderlake: Add TBT PCIe root ports enablement	Bernardo Perez Priego
2021-06-16	soc/intel/alderlake: Make use of is_devfn_enabled() function	Subrata Banik
2021-06-07	soc/intel: Drop unused lpss functions	Furquan Shaikh
2021-05-18	soc/intel/alderlake: mb/intel/sm: Add tcss code	Deepti Deshatty
2021-04-16	soc/intel/alderlake: Allow devicetree to fill UPD related to TCSS OC	Maulik V Vaghela
2021-03-15	soc/intel/alderlake: Add CNVi Bluetooth flag at devicetree entry	Cliff Huang
2021-03-08	soc/intel/alderlake: Set LidStatus UPD if RUN_FSP_GOP selected	Ronak Kanabar
2021-02-05	soc/intel/alderlake: Refactor PCIE port config	Eric Lai
2021-01-10	soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs	Subrata Banik
2021-01-06	soc/intel/alderlake: Update CPU microcode patch base address/size	Subrata Banik
2020-10-03	soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage	Subrata Banik