diff options
| author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-07-19 15:35:47 -0600 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-10 19:38:46 +0000 |
| commit | e2b8f30beeb1b63e1b94dccc1a96bed5c9a2c63e (patch) | |
| tree | a95616939edb85010ad7dc2d679daa6518d61b15 /src/soc/intel/alderlake/fsp_params.c | |
| parent | 6cf79d9d14aa6be9bc5594dcf4040da8cbb87544 (diff) | |
soc/intel/alderlake: Set LpmStateEnableMask UPD
Use the get_supported_lpm_states() function to set the respective FSP
UPD.
TEST=with patchtrain on brya0,
/sys/kernel/debug/pmc_core/substate_requirements shows only the
substates that are applicable to the design (S0i2.0, S0i3.0).
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5bb8b3671e78c5f2706db2d3a21b25cf90a14275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/alderlake/fsp_params.c')
| -rw-r--r-- | src/soc/intel/alderlake/fsp_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 7e1afde38b..107d22e9e4 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -15,6 +15,7 @@ #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <intelblocks/tcss.h> +#include <soc/cpu.h> #include <soc/gpio_soc_defs.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -614,6 +615,8 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, /* VrConfig Settings for IA and GT domains */ for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); + + s_cfg->LpmStateEnableMask = get_supported_lpm_mask(); } static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, |