| Age | Commit message (Expand) | Author |
|---|---|---|
| 2015-12-21 | imgtec/pistachio: DDR2, DDR3: DLL reset set | Ionela Voinescu |
| 2015-12-21 | imgtec/pistachio: DDR2, DDR3: DQS gate early | Ionela Voinescu |
| 2015-10-31 | tree: drop last paragraph of GPL copyright header | Patrick Georgi |
| 2015-06-12 | pistachio: add DDR3 initialization code | Ionela Voinescu |
| 2015-06-12 | pistachio: Use passive windowing as DQS gating scheme | Ionela Voinescu |
| 2015-06-10 | pistachio: sort included header files | Ionela Voinescu |
| 2015-05-21 | Remove address from GPLv2 headers | Patrick Georgi |
| 2015-04-22 | imgtec/pistachio: DDR reads return to controller with no bubbles | Ionela Voinescu |
| 2015-04-22 | imgtec/pistachio: DDR row/bank/column mapping | Ionela Voinescu |
| 2015-04-21 | pistachio: Remove 50% DDR bandwidth restriction | Ionela Voinescu |
| 2015-04-21 | pistachio: Decrease DDR ODT from 75R to 50R | Ionela Voinescu |
| 2015-04-21 | pistachio: clean DDR2 initialization code | Ionela Voinescu |
| 2015-04-17 | pistachio: add DDR2 initialization code | Ionela Voinescu |
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index : coreboot.git | |
| my copy of coreboot | User & |
| summaryrefslogtreecommitdiff |