diff options
author | Ionela Voinescu <ionela.voinescu@imgtec.com> | 2015-05-21 13:29:45 +0100 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2015-12-21 02:05:17 +0100 |
commit | 6b95406ff3d44679d2e0139236c134655b12b927 (patch) | |
tree | 03248c5604b395f791beaeaf3de050ffb4653ac9 /src/soc/imgtec/pistachio/ddr2_init.c | |
parent | f6d3bd4815d2d442eb3cdf418ba3074134e5bd7d (diff) |
imgtec/pistachio: DDR2, DDR3: DQS gate early
Switching on DQS Gate Early and DQS Gate Extension with
500R DQS/DSQN Resistors. This setup was recommended by
Synopsys.
Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.
Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/imgtec/pistachio/ddr2_init.c')
-rw-r--r-- | src/soc/imgtec/pistachio/ddr2_init.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/src/soc/imgtec/pistachio/ddr2_init.c b/src/soc/imgtec/pistachio/ddr2_init.c index e21b79b815..322d241164 100644 --- a/src/soc/imgtec/pistachio/ddr2_init.c +++ b/src/soc/imgtec/pistachio/ddr2_init.c @@ -143,8 +143,8 @@ int init_ddr2(void) * 2 ZUEN Def 1 * 3 LPIOPD DEf 1 0 * 4 LPDLLPD DEf 1 0 - * 7:5 DQSGX DQS Extention 000 - * 10:8 DQSGE DQS Early Gate + * 7:5 DQSGX DQS Extention set to 1 - advised by Synopsys + * 10:8 DQSGE DQS Early Gate - 1 - advised by Sysnopsys * 11 NOBUB No Bubbles, adds latency 1 * 12 FXDLAT Fixed Read Latency 0 * 15:13 Reserved @@ -159,7 +159,9 @@ int init_ddr2(void) * 30 RSTOE RST# Output Enable 1 * 31 CKEOE CKE Output Enable 1 */ - write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000807); + write32(DDR_PHY + DDRPHY_DSGCR_OFFSET, 0xF2000927); + /* Sysnopsys advised 500R pullup/pulldown DQS DQSN */ + write32(DDR_PHY + DDRPHY_DXCCR_OFFSET, 0x00000C40); /* DTPR0 : DRAM Timing Params 0 * 1:0 tMRD 2 * 4:2 tRTP 3 @@ -235,6 +237,10 @@ int init_ddr2(void) /* PGSR : Wait for DRAM Init Done */ if (wait_for_completion(DDR_PHY + DDRPHY_PGSR_OFFSET, 0x0000001F)) return DDR_TIMEOUT; + /* Disable Impedance Calibration */ + write32(DDR_PHY + DDRPHY_ZQ0CR0_OFFSET, 0x3000014A); + write32(DDR_PHY + DDRPHY_ZQ1CR0_OFFSET, 0x3000014A); + /* DF1STAT0 : wait for DFI_INIT_COMPLETE */ if (wait_for_completion(DDR_PCTL + DDR_PCTL_DFISTAT0_OFFSET, 0x00000001)) @@ -315,10 +321,10 @@ int init_ddr2(void) * DQS additional turn around Rank 2 Rank (1 Rank) Def 1 */ write32(DDR_PCTL + DDR_PCTL_TDQS_OFFSET, 0x00000001); - /*TRTW : Read to Write turn around time Def 2 + /*TRTW : Read to Write turn around time Def 3 * Actual gap t_bl + t_rtw */ - write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000002); + write32(DDR_PCTL + DDR_PCTL_TRTW_OFFSET, 0x00000003); /* TCKE : CKE min pulse width DEf 3 */ write32(DDR_PCTL + DDR_PCTL_TCKE_OFFSET, 0x00000003); /* |