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2017-11-10src/soc/amd/stoneyridge/southbridge.h: Fix prototypesRichard Spiegel
Some prototypes types don't match the actual function type, though there's no error message due to the types being alias. For clarity, types should match between prototypes and actual functions. BUG=b:68007655 Change-Id: I9573a68f7153dbbad2fc6551d5dab000760c871e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Martin Roth <martinroth@google.com>
2017-11-09src/soc/amd/stoneyridge/southbridge.h: Remove unused prototypesRichard Spiegel
Remove unused s3_resume_init_data prototype from southbridge,h BUG=b:68007655 Change-Id: If022f873813070aac6cc9090c2212178a4e66354 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Add PSP definitions southbridge and iomapMarshall Dawson
Define the PSP's BAR3 and BAR3 enable bit. Define a default base address for BAR3. Change-Id: I59a0ec59b7c6bbc6468b3096ec8d025832349f44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-08amd/stoneyridge: Add northbridge register macrosMarshall Dawson
Add helpers for determining the D18F1 offset for MMIO base and limit, and I/O base/limit registers. Change-Id: I3f61bff00b8f3ada3e1bbfb163e1f223708bd47d Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-06soc/amd/stoneyridge: consolidate addresses in iomap.hAaron Durbin
Take the existing scattered around address space defines and put them in iomap.h. Change-Id: I78aa1370b05d3e2f90d43f754076b81734cccf7f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22319 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-06soc/amd/stoneyridge: start header file for iomapAaron Durbin
Create a new header file, iomap.h, which serves as a single place for providing the address space definitions. Remove the amd_defs.h file that had a single define in it. Change-Id: I1b1aaa8c5d60d670c272ac7131faeb6b3edc1968 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22318 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-11-04soc/amd/stoneyridge: fix incorrect constants in macrosAaron Durbin
Hex constants need '0x' prefix. Clearly these weren't being used, but they should be fixed properly. Change-Id: I43ab90500b6d5bc31db7ebd1c675d651c8971b87 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/22315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-11-04sb and soc: Enforce correct offset of member "chromeos" in global_nvs_tJonathan Neuschäfer
The padding has recently been broken in commit 90ebf96df5 ("soc/intel/skylake: Add GNVS variables and include SGX ASL") and fixed again in commit af88398887 ("soc/intel/skylake: Fix broken GNVS offset for chromeos"). Avoid this bug in the future. Change-Id: I1bf3027bba239c8747ad26a3130a7e047d3b8c94 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/22229 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-11-01amd/stoneyridge: Add pci_dev macrosMarshall Dawson
Add #defines that will allow easy use of PCI devices across stages. Future work can convert soc/amd/stoneyridge to use these and clean up the DEV_D18F4 macro still in place. Change-Id: I78c297d9610009e7b9e2233984e1a167f0ab88c7 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01amd/stoneyridge: Add definitions for various NB registersMarshall Dawson
Add #define values for the first MMIO base/limit, the first I/O base/limit, and VGA enable registers. Change-Id: I2c209224d356cf3f83a0ddb37974831611a89760 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01amd/stoneyridge: Consolidate duplicate commentMarshall Dawson
Change-Id: Ifaf8815dff595eb723f1b864b8f827768cb43847 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-11-01amd/stoneyridge: Add definition for HPET to southbridgeMarshall Dawson
Add #define values for the HPET device. In Stoney Ridge, the base address is fixed and cannot be relocated. Change-Id: Id36fd9ecc90d54a92144f2cca7cec6d84abfdabd Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/22242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-22soc/amd/stoneyridge: Remove duplicate macros in pci_devs.hChris Ching
BUG=b:68046770 TEST=build Change-Id: Iea0df0dc7baa384cac45a300fdcc8d59f0aac798 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-10-20stoneyridge: Add SCI/GPE configurationMarc Jones
Add functions for configuring the GPE ACPI SCI events. BUG=b:63268311 BRANCH=none TEST=With the Kahlee GPE setup patch, test lidswitch powers the device on and off at the login screen. Change-Id: I5c282268edbd7b92a3f2ca7c72896406c8f8512f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/22095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-19soc/amd/stoneyridge: Use macros for PCI_DEVFN callsChris Ching
* Change all calls to PCI_DEVFN to macros * Remove CBB and CDB Kconfig since these are static for stoneyridge BUG=b:62200746 TEST=build Change-Id: I001c4ccd0ad7cf2047870b3618e13642144ddf56 Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/22110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-19soc/amd/stoneyridge: Replace magic registersRichard Spiegel
Replace southbridge registers and register values from magic numbers to literals, provided these registers are currently defined publicly or in NDA datasheet. Registers available only internally to AMD are left unchanged. BUG=b:62199625 Change-Id: I9187ba1c41ebb1201ddc177e8184672c60cd5f5d Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/21767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-10-15amd/stoneyridge: Add function to find PmControl registerMarshall Dawson
Find the PmControl register's I/O address by checking the hardware in PMx62. Don't rely on the address being the coreboot default. PmControl is the first register in the AcpiPm1CntBlk. Change-Id: Ibb608dcaa7801af067d6edd86f92c117c2ac08a6 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Change SMM setup functionsMarshall Dawson
Remove the APMC-specific initialization call. Make the function which programs the event type not static and call it from the southbridge.c file. Change-Id: I1e3cf898637720fa835de0a6e735c6a65fe2d3a2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Add PM defintions to southbridge.hMarshall Dawson
Change-Id: I2534ab34f8a8d151e80004ee05d3061f013316b0 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21747 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Refactor SMI handlerMarshall Dawson
Rewrite the handler to be more compact and extendable. The old functionality is duplicated after the rewrite. All SMI source registers (except for SmiSciStatus) behave identically so these are consolidated. Register 0x80 contains sources 0-31, 0x81 sources 32-63, and so on. Create a table of mini-handlers to be supported in the soc directory. As SMI sources are discovered, attempt to find the corresponding handler and then execute it. Change-Id: Ic7050ecf65c2af036fe297f429a0bbdc709ad4c1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21746 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Check SMI command address before readingMarshall Dawson
Use the currently programmed address of the SMI command port before checking the passed command. This ensures we're reading the right port in case the port was relocated without our knowledge. Change-Id: I8a3ca285d3a9afd4a107cd471c202abf03f372ac Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02amd/stoneyridge: Move pm/smi_read/write functions to util fileMarshall Dawson
Pull all pm_read and write, smi_read and write variants into a single file. Change-Id: I87d17361f923a60c95ab66e150445a6a0431b772 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Add pm_read32 and pm_write32 to southbridgeMarshall Dawson
Duplicate existing pm_read and pm_write and create 32-bit register access functions. Change-Id: I916130a229dc7cef8dae1faf00a38501d3939979 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21749 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Fix pm_read16 argument sizeMarshall Dawson
Make pm_read16() consistent with the other PM register access functions. Change-Id: Iba017b8090ed07d8684cc7f396a3e9a942b3ad95 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21748 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-10-02amd/stoneyridge: Add more SMM definitionsMarshall Dawson
Change-Id: I4c8069a18ea430ec6e66d41879c8e77f1ef2b340 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2017-09-30amd/stoneyridge: Use generic SMM command port valuesMarshall Dawson
Remove the old Hudson-specific SMM command port definitions and use the ones in cpu/x86/smm.h. Change-Id: I3de9a178e5f189ac1dbc921e41b69d47e3796a4f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27soc/amd/stoneyridge: Add postcar stageMarshall Dawson
Insert a postcar stage for Stoney Ridge and move romstage's CAR teardown there. The AMD cache-as-ram teardown procedure currently uses a wbinvd instruction to send CAR contents to DRAM backing. This allows preserving stack contents and CAR globals after the teardown happens, but likely results in memory corruption during S3 resume. Due to the current base of the DCACHE region, reverting to an invd instruction will break the detection mechanism for CAR migrated variables. Using postcar avoids this problem. The current behavior of AGESA is to set up all cores' MTRRs during the AmdInitPost() entry point. This implementation takes control back and causes postcar's _start to clear all settings and set attributes only for the BIOS flash device, TSEG, and enough space below cbmem_top to load and run ramstage. BUG=b:64768556 Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20966 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27amd/stoneyridge: Enable SMM in TSEGMarshall Dawson
Add necessary features to allow mp_init_with_smm() to install and relocate an SMM handler. SMM region functions are added to easily identify the SMM attributes. Adjust the neighboring cbmem_top() rounding downward to better reflect the default TSEG size. Add relocation attributes to be set by each core a relocation handler. Modify the definition of smi_southbridge_handler() to match TSEG prototype. BUG=b:62103112 Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21501 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-27amd/stoneyridge: Convert MP init to mp_init_with_smmMarshall Dawson
Change the Stoney Ridge SOC to a more modern method for setting up the multiple cores. Add a new cpu.c file for most of the processor initiliazation. Build mp_ops with the necessary callbacks. Note also that this patch removes cpu_bus_scan. Rather than manually find CPUs and add them to the devicetree, allow this to be done automatically in the generic mp_init.c file. SMM information is left blank in mp_ops to avoid having mp_init.c install a handler at this time. A later patch will add TSEG SMM capabilities for the APU. This patch also contains a hack to mask the behavior of AGESA which configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost. The hack immediately changes all WB variable MTRRs, on the BSP, to UC so that all writes to memory space will make it to the DRAM. BUG=b:66200075 Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21498 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27google/kahlee: Fix GPIO ASLMarc Jones
Use a single define and set the CROS GPIO ASL device to match the Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN field in the GPIO ASL. This addresses the TEST indicated below. BUG=b:65597554 BRANCH=none TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030. Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27amd/stoneyridge: Refactor GPIO functionsMarc Jones
Refactor the GPIO functions to use GPIO numbers. This is more consistent with other GPIO code in coreboot. BUG=b:66462235 BRANCH=none TEST=Build and boot Kahlee Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-19amd/stoneyridge: Add northbridge definitionsMarshall Dawson
Begin adding D18F1 definitions to northbridge.h. Change-Id: I4fa2f9a4af8fbb3c2919ffb5dca34cbe333bc958 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21562 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-13amd/stoneyridge: Remove duplicate PCI definitionsMarshall Dawson
There were two copies of the same definitions in the file. Change-Id: Iafb10476f32505f6b4ad7b5ba6fa5de2c4648836 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/21333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-09-06soc/amd/stoneyridge: Use __packedJonathan Neuschäfer
__packed has been introduced in commit 6a00113de8 ("Rename __attribute__((packed)) --> __packed"). Use it. Change-Id: Ie654567ebff884b911de10bd9fef605436e72af8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-08-28soc/amd: Standardize guards on header filesMartin Roth
The guards in the header files were inconsistent. Some had no leading or trailing underscores, some had one, some had both leading and trailing. Change all to double leading & trailing underscores. Change all comments to have a space before them instead of tabs BUG=b:62235990 Test=Build Kahlee Change-Id: I4466df529ab201c922096a31d7438381778b582f Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25amd/pi/hudson: Fix FCH ECMartin Roth
Move the fchec.h files, which do not seem mainboard specific, out of the mainboard directories into the southbridge/soc directories. Change-Id: Idd271c6ab618aa4badf81c702212e7de35317021 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-08-25soc/amd/stoneyridge: Move oem_fan_control()Kyösti Mälkki
While at it, replace LibAmdMemFill() with memset(). Change-Id: I770cab446add8f305f02e365e7c9763df88cd958 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21192 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-14stoneyridge: Rename hudson to southbridgeMarc Jones
Simplify funciton names and remove reference to hudson in stoneyridge. The southbridge in Stoney Ridge is Kern and hudson naming is no longer accurate. BUG=b:62200157 BRANCH=none TEST=Build and booted on Kahlee. Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-08-04soc/amd/stoneyridge: Use generic gpio libraryMarc Jones
Use the genric GPIO library. Add the required functions. Also, update the Kahlee mainboard dependency to match. Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20543 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31soc/amd/stoneyridge: Add GPIO functions to romstageMarc Jones
A mainboard may access GPIO in romstage. Change-Id: Id380c6570943ce2a0bf6112d62cc91aeae283fcf Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-31soc/amd/stoneyridge: Fix GPIO bank1 control definitionMarshall Dawson
Change-Id: Ia6c7357ba0c581dc46d173f462efce181847a4e1 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20526 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31soc/amd/stoneyridge: Move ACPI MADT table to socMarc Jones
Move the mainboard MADT tables to generic soc ACPI code. Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20277 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-07-31soc/amd/stoneyridge: Add GNVSMarc Jones
Add ACPI asl for global non-volatile storage (GNVS). Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/20275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-07-27soc/amd/common: Convert to C_ENVIRONMENT_BOOTBLOCKMarshall Dawson
Add dedicated CAR setup and teardown functions and Kconfig options to force their inclusion into the build. The .S files are mostly duplicated code from the old cache_as_ram.inc file. The .S files use global proc names in anticipation for use with the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE. Move the mainboard romstage functionality into the soc directory and change the function name to be compatible with the call from assembly_entry.S. Drop the BIST check like other devices. Move InitReset and InitEarly to bootblock. These AGESA entry points set some default settings, and release/recapture the AP cores. There are currently some early dependencies on InitReset. Future work should include: * Pull the necessary functionality from InitReset into bootblock * Move InitReset and InitEarly to car_stage_entry() and out of bootblock - Add a mechanism for the BSP to give the APs an address to call and skip most of bootblock and verstage (when available) (1) - Reunify BiosCallOuts.c and OemCustomize.c (1) During the InitReset call, the BSP enables the APs by setting core enable bits in F18F0x1DC and APs begin fetching/executing from the reset vector. The BSP waits for all APs to also reach InitReset, where they enter an endless loop. The BSP sends a command to them to execute a HLT instruction and the BSP eventually returns from InitReset. The goal would be to preserve this process but prevent APs from rerunning early code. Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19755 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-07-12soc/amd/stoneyridge: Update header guards and includesMarshall Dawson
Rename the guard to better match the new directory structure. Add include files containing typedefs used in the file. Change-Id: I5fe23ce6994603b0ace99fd6ffc5f3eded2880af Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20525 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-28soc/amd/stoneyridge: Revise pci_devs.h fileMarshall Dawson
Now that pci_devs.h is part of soc/ and not used for multiple southbridges: * Remove devices not present in the Stoney Ridge APU * Complete the list to include additional devices besides those in the FCH. BUG=chrome-os-partner:62578372 Change-Id: I1cd2d5e41473f362bbfd28ee93788a292bc33991 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20370 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2017-06-28soc/amd/stoneyridge: Fix device IDsMarshall Dawson
Update pci_devs.h to the correct IDs for Stoney Ridge. BUG=chrome-os-partner:62578372 Change-Id: Ic1a7fe8d95c34b80e21cc089168732372d9690a3 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/20200 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/stoneyridge: Remove PCIe-PCI bridgeMarshall Dawson
The Stoney Ridge does not contain this bridge like some of the older Hudson FCHs. Remove this support from the source. This moves the Stoney Ridge IRQ setup to the southbridge file, hudson.c. BUG=chrome-os-partner:62580062 Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/20198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-27soc/amd/stoneyridge: Fix most checkpatch errorsMarshall Dawson
Correct the majority of reported errors and mark most of the remaining ones as todo. (Some of the lines requiring a >80 break are indented too much currently.) Some of the alignment in hudson.h still causes checkpatch errors, but this is intentionally left as-is. Also make other misc. changes, e.g. consistency in lower-case for hex values, using defined values, etc. These changes were confirmed to cause no changes in a Gardenia build. No other improvements were made, e.g. changing to helper functions, or converting functions like __outbyte(). BUG=chrome-os-partner:622407746 Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/19986 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc/amd/stoneyridge: Add northbridge supportMarc Jones
Copy northbridge files from northbridge/amd/pi/00670F00 to soc/amd/stoneyridge and soc/amd/common. Changes: - update chip_ops and device_ops - remove multi-node support - clean up Kconfig and Makefile Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19724 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-06-26soc: Add AMD Stoney Ridge southbridge codeMarc Jones
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This is the first of a series of patches to migrate Stoney Ridge support from cpu, northbridge, and southbridge to soc/ Changes: - add soc/amd/stoneyridge and soc/amd/common - remove all other Husdon versions - update include paths, etc - clean up Kconfig and Makefile - create chip.c to contain chip_ops Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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