soc: Add AMD Stoney Ridge southbridge code

Copy the Hudson/Kern code from southbridge/amd/pi/hudson.  This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/

Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops

Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

8 files changed, 720 insertions, 0 deletions

diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h
new file mode 100644
index 0000000000..361c06f5b7
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef AMD_PCI_INT_DEFS_H
+#define AMD_PCI_INT_DEFS_H
+
+/*
+ * PIRQ and device routing - these define the index
+ * into the FCH PCI_INTR 0xC00/0xC01 interrupt
+ * routing table
+ */
+
+#define PIRQ_NC		0x1F	/* Not Used */
+#define PIRQ_A		0x00	/* INT A */
+#define PIRQ_B		0x01	/* INT B */
+#define PIRQ_C		0x02	/* INT C */
+#define PIRQ_D		0x03	/* INT D */
+#define PIRQ_E		0x04	/* INT E */
+#define PIRQ_F		0x05	/* INT F */
+#define PIRQ_G		0x06	/* INT G */
+#define PIRQ_H		0x07	/* INT H */
+#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings - See FCH Spec */
+#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
+#define PIRQ_MISC1	0x0A	/* Miscellaneous1 IRQ Settings */
+#define PIRQ_MISC2	0x0B	/* Miscellaneous2 IRQ Settings */
+#define PIRQ_SIRQA	0x0C	/* Serial IRQ INTA */
+#define PIRQ_SIRQB	0x0D	/* Serial IRQ INTB */
+#define PIRQ_SIRQC	0x0E	/* Serial IRQ INTC */
+#define PIRQ_SIRQD	0x0F	/* Serial IRQ INTD */
+#define PIRQ_SCI	0x10	/* SCI IRQ */
+#define PIRQ_SMBUS	0x11	/* SMBUS	14h.0 */
+#define PIRQ_ASF	0x12	/* ASF */
+#define PIRQ_HDA	0x13	/* HDA		14h.2 */
+#define PIRQ_FC		0x14	/* FC */
+#define PIRQ_GEC	0x15	/* GEC */
+#define PIRQ_PMON	0x16	/* Performance Monitor */
+#define PIRQ_SD 	0x17	/* SD */
+#define PIRQ_IMC0	0x20	/* IMC INT0 */
+#define PIRQ_IMC1	0x21	/* IMC INT1 */
+#define PIRQ_IMC2	0x22	/* IMC INT2 */
+#define PIRQ_IMC3	0x23	/* IMC INT3 */
+#define PIRQ_IMC4	0x24	/* IMC INT4 */
+#define PIRQ_IMC5	0x25	/* IMC INT5 */
+#define PIRQ_OHCI1	0x30	/* USB OHCI	12h.0 */
+#define PIRQ_EHCI1	0x31	/* USB EHCI	12h.2 */
+#define PIRQ_OHCI2	0x32	/* USB OHCI	13h.0 */
+#define PIRQ_EHCI2	0x33	/* USB EHCI	13h.2 */
+#define PIRQ_OHCI3	0x34	/* USB OHCI	16h.0 */
+#define PIRQ_EHCI3	0x35	/* USB EHCI	16h.2 */
+#define PIRQ_OHCI4	0x36	/* USB OHCI	14h.5 */
+#define PIRQ_IDE	0x40	/* IDE		14h.1 */
+#define PIRQ_SATA	0x41	/* SATA		11h.0 */
+
+#define FCH_INT_TABLE_SIZE 0x76
+#define PIRQ_GPIO	0x62	/* GPIO Controller Interrupt */
+#define PIRQ_I2C0	0x70
+#define PIRQ_I2C1	0x71
+#define PIRQ_I2C2	0x72
+#define PIRQ_I2C3	0x73
+#define PIRQ_UART0	0x74
+#define PIRQ_UART1	0x75
+
+#endif /* AMD_PCI_INT_DEFS_H */
diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
new file mode 100644
index 0000000000..30ab0d4839
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef AMD_PCI_INT_TYPES_H
+#define AMD_PCI_INT_TYPES_H
+
+const char * intr_types[] = {
+	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
+	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
+	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t",
+	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
+	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
+	[0x7F] = "RSVD\t",
+	[0x40] = "IDE\t", "SATA\t",
+	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
+	[0x62] = "GPIO\t",
+	[0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t",
+};
+
+#endif /* AMD_PCI_INT_TYPES_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
new file mode 100644
index 0000000000..22c0fba123
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _STONEYRIDGE_GPIO_H_
+#define _STONEYRIDGE_GPIO_H_
+
+#include <soc/amd/common/amd_defs.h>
+#include <types.h>
+
+#define CROS_GPIO_DEVICE_NAME	"AmdKern"
+
+#define GPIO_PIN_STS		(1 << 16)
+#define GPIO_OUTPUT_VALUE	(1 << 22)
+#define GPIO_OUTPUT_ENABLE	(1 << 23)
+
+/* GPIO_0 - GPIO_62 */
+#define GPIO_BANK0_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1500)
+#define   GPIO_0	(GPIO_BANK0_CONTROL + 0x00)
+#define   GPIO_1	(GPIO_BANK0_CONTROL + 0x04)
+#define   GPIO_2	(GPIO_BANK0_CONTROL + 0x08)
+#define   GPIO_3	(GPIO_BANK0_CONTROL + 0x0C)
+#define   GPIO_4	(GPIO_BANK0_CONTROL + 0x10)
+#define   GPIO_5	(GPIO_BANK0_CONTROL + 0x14)
+#define   GPIO_6	(GPIO_BANK0_CONTROL + 0x18)
+#define   GPIO_7	(GPIO_BANK0_CONTROL + 0x1C)
+#define   GPIO_8	(GPIO_BANK0_CONTROL + 0x20)
+#define   GPIO_9	(GPIO_BANK0_CONTROL + 0x24)
+#define   GPIO_10	(GPIO_BANK0_CONTROL + 0x28)
+#define   GPIO_11	(GPIO_BANK0_CONTROL + 0x2C)
+#define   GPIO_12	(GPIO_BANK0_CONTROL + 0x30)
+#define   GPIO_13	(GPIO_BANK0_CONTROL + 0x34)
+#define   GPIO_14	(GPIO_BANK0_CONTROL + 0x38)
+#define   GPIO_15	(GPIO_BANK0_CONTROL + 0x3C)
+#define   GPIO_16	(GPIO_BANK0_CONTROL + 0x40)
+#define   GPIO_17	(GPIO_BANK0_CONTROL + 0x44)
+#define   GPIO_18	(GPIO_BANK0_CONTROL + 0x48)
+#define   GPIO_19	(GPIO_BANK0_CONTROL + 0x4C)
+#define   GPIO_20	(GPIO_BANK0_CONTROL + 0x50)
+#define   GPIO_21	(GPIO_BANK0_CONTROL + 0x54)
+#define   GPIO_22	(GPIO_BANK0_CONTROL + 0x58)
+#define   GPIO_23	(GPIO_BANK0_CONTROL + 0x5C)
+#define   GPIO_24	(GPIO_BANK0_CONTROL + 0x60)
+#define   GPIO_25	(GPIO_BANK0_CONTROL + 0x64)
+#define   GPIO_26	(GPIO_BANK0_CONTROL + 0x68)
+#define   GPIO_39	(GPIO_BANK0_CONTROL + 0x9C)
+#define   GPIO_42	(GPIO_BANK0_CONTROL + 0xA8)
+
+/* GPIO_64 - GPIO_127 */
+#define GPIO_BANK1 (CONTROL AMD_SB_ACPI_MMIO_ADDR + 0x1600)
+#define   GPIO_64	(GPIO_BANK1_CONTROL + 0x00)
+#define   GPIO_65	(GPIO_BANK1_CONTROL + 0x04)
+#define   GPIO_66	(GPIO_BANK1_CONTROL + 0x08)
+#define   GPIO_67	(GPIO_BANK1_CONTROL + 0x0C)
+#define   GPIO_68	(GPIO_BANK1_CONTROL + 0x10)
+#define   GPIO_69	(GPIO_BANK1_CONTROL + 0x14)
+#define   GPIO_70	(GPIO_BANK1_CONTROL + 0x18)
+#define   GPIO_71	(GPIO_BANK1_CONTROL + 0x1C)
+#define   GPIO_72	(GPIO_BANK1_CONTROL + 0x20)
+#define   GPIO_74	(GPIO_BANK1_CONTROL + 0x28)
+#define   GPIO_75	(GPIO_BANK1_CONTROL + 0x2C)
+#define   GPIO_76	(GPIO_BANK1_CONTROL + 0x30)
+#define   GPIO_84	(GPIO_BANK1_CONTROL + 0x50)
+#define   GPIO_85	(GPIO_BANK1_CONTROL + 0x54)
+#define   GPIO_86	(GPIO_BANK1_CONTROL + 0x58)
+#define   GPIO_87	(GPIO_BANK1_CONTROL + 0x5C)
+#define   GPIO_88	(GPIO_BANK1_CONTROL + 0x60)
+#define   GPIO_89	(GPIO_BANK1_CONTROL + 0x64)
+#define   GPIO_90	(GPIO_BANK1_CONTROL + 0x68)
+#define   GPIO_91	(GPIO_BANK1_CONTROL + 0x6C)
+#define   GPIO_92	(GPIO_BANK1_CONTROL + 0x70)
+#define   GPIO_93	(GPIO_BANK1_CONTROL + 0x74)
+#define   GPIO_95	(GPIO_BANK1_CONTROL + 0x7C)
+#define   GPIO_96	(GPIO_BANK1_CONTROL + 0x80)
+#define   GPIO_97	(GPIO_BANK1_CONTROL + 0x84)
+#define   GPIO_98	(GPIO_BANK1_CONTROL + 0x88)
+#define   GPIO_99	(GPIO_BANK1_CONTROL + 0x8C)
+#define   GPIO_100	(GPIO_BANK1_CONTROL + 0x90)
+#define   GPIO_101	(GPIO_BANK1_CONTROL + 0x94)
+#define   GPIO_102	(GPIO_BANK1_CONTROL + 0x98)
+#define   GPIO_113	(GPIO_BANK1_CONTROL + 0xC4)
+#define   GPIO_114	(GPIO_BANK1_CONTROL + 0xC8)
+#define   GPIO_115	(GPIO_BANK1_CONTROL + 0xCC)
+#define   GPIO_116	(GPIO_BANK1_CONTROL + 0xD0)
+#define   GPIO_117	(GPIO_BANK1_CONTROL + 0xD4)
+#define   GPIO_118	(GPIO_BANK1_CONTROL + 0xD8)
+#define   GPIO_119	(GPIO_BANK1_CONTROL + 0xDC)
+#define   GPIO_120	(GPIO_BANK1_CONTROL + 0xE0)
+#define   GPIO_121	(GPIO_BANK1_CONTROL + 0xE4)
+#define   GPIO_122	(GPIO_BANK1_CONTROL + 0xE8)
+#define   GPIO_126	(GPIO_BANK1_CONTROL + 0xF8)
+
+/* GPIO_128 - GPIO_183 */
+#define GPIO_BANK2_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1700)
+#define   GPIO_129	(GPIO_BANK2_CONTROL + 0x04)
+#define   GPIO_130	(GPIO_BANK2_CONTROL + 0x08)
+#define   GPIO_131	(GPIO_BANK2_CONTROL + 0x0C)
+#define   GPIO_132	(GPIO_BANK2_CONTROL + 0x10)
+#define   GPIO_133	(GPIO_BANK2_CONTROL + 0x14)
+#define   GPIO_134	(GPIO_BANK2_CONTROL + 0x18)
+#define   GPIO_135	(GPIO_BANK2_CONTROL + 0x1C)
+#define   GPIO_136	(GPIO_BANK2_CONTROL + 0x20)
+#define   GPIO_137	(GPIO_BANK2_CONTROL + 0x24)
+#define   GPIO_138	(GPIO_BANK2_CONTROL + 0x28)
+#define   GPIO_139	(GPIO_BANK2_CONTROL + 0x2C)
+#define   GPIO_140	(GPIO_BANK2_CONTROL + 0x30)
+#define   GPIO_141	(GPIO_BANK2_CONTROL + 0x34)
+#define   GPIO_142	(GPIO_BANK2_CONTROL + 0x38)
+#define   GPIO_143	(GPIO_BANK2_CONTROL + 0x3C)
+#define   GPIO_144	(GPIO_BANK2_CONTROL + 0x40)
+#define   GPIO_145	(GPIO_BANK2_CONTROL + 0x44)
+#define   GPIO_146	(GPIO_BANK2_CONTROL + 0x48)
+#define   GPIO_147	(GPIO_BANK2_CONTROL + 0x4C)
+#define   GPIO_148	(GPIO_BANK2_CONTROL + 0x50)
+
+typedef uint32_t gpio_t;
+
+int gpio_get(gpio_t gpio_num);
+
+#endif	/* _STONEYRIDGE_GPIO_H_ */
diff --git a/src/soc/amd/stoneyridge/include/soc/hudson.h b/src/soc/amd/stoneyridge/include/soc/hudson.h
new file mode 100644
index 0000000000..bfe506edd1
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/hudson.h
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef STONEYRIDGE_H
+#define STONEYRIDGE_H
+
+#include <arch/io.h>
+#include <types.h>
+#include <device/pci_ids.h>
+#include <device/device.h>
+#include "chip.h"
+
+/* Offsets from ACPI_MMIO_BASE
+ * This is defined by AGESA, but we don't include AGESA headers to avoid
+ * polluting the namespace.
+ */
+#define PM_MMIO_BASE			0xfed80300
+
+/* Power management index/data registers */
+#define BIOSRAM_INDEX			0xcd4
+#define BIOSRAM_DATA			0xcd5
+#define PM_INDEX			0xcd6
+#define PM_DATA				0xcd7
+#define PM2_INDEX			0xcd0
+#define PM2_DATA			0xcd1
+
+#define PM_ACPI_MMIO_EN			0x24
+#define PM_SERIRQ_CONF			0x54
+#define PM_EVT_BLK			0x60
+#define PM1_CNT_BLK			0x62
+#define PM_TMR_BLK			0x64
+#define PM_CPU_CTRL			0x66
+#define PM_GPE0_BLK			0x68
+#define PM_ACPI_SMI_CMD			0x6A
+#define PM_ACPI_CONF			0x74
+#define PM_PMIO_DEBUG			0xD2
+#define PM_MANUAL_RESET			0xD3
+#define PM_HUD_SD_FLASH_CTRL		0xE7
+#define PM_YANG_SD_FLASH_CTRL		0xE8
+#define PM_PCIB_CFG			0xEA
+
+#define STONEYRIDGE_ACPI_IO_BASE		CONFIG_STONEYRIDGE_ACPI_IO_BASE
+#define ACPI_PM_EVT_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */
+#define ACPI_PM1_CNT_BLK	(STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */
+#define ACPI_PM_TMR_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
+#define ACPI_GPE0_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x10) /* 8 bytes */
+#define ACPI_CPU_CONTROL	(STONEYRIDGE_ACPI_IO_BASE + 0x08) /* 6 bytes */
+
+#define ACPI_SMI_CTL_PORT		0xb2
+#define ACPI_SMI_CMD_CST_CONTROL	0xde
+#define ACPI_SMI_CMD_PST_CONTROL	0xad
+#define ACPI_SMI_CMD_DISABLE		0xbe
+#define ACPI_SMI_CMD_ENABLE		0xef
+#define ACPI_SMI_CMD_S4_REQ		0xc0
+
+#define REV_STONEYRIDGE_A11			0x11
+#define REV_STONEYRIDGE_A12			0x12
+
+#define SPIROM_BASE_ADDRESS_REGISTER	0xA0
+#define   ROUTE_TPM_2_SPI		BIT(3)
+#define   SPI_ROM_ENABLE		0x02
+#define   SPI_BASE_ADDRESS		0xFEC10000
+
+#define LPC_IO_PORT_DECODE_ENABLE	0x44
+#define   DECODE_ENABLE_PARALLEL_PORT0	BIT(0)
+#define   DECODE_ENABLE_PARALLEL_PORT1	BIT(1)
+#define   DECODE_ENABLE_PARALLEL_PORT2	BIT(2)
+#define   DECODE_ENABLE_PARALLEL_PORT3	BIT(3)
+#define   DECODE_ENABLE_PARALLEL_PORT4	BIT(4)
+#define   DECODE_ENABLE_PARALLEL_PORT5	BIT(5)
+#define   DECODE_ENABLE_SERIAL_PORT0	BIT(6)
+#define   DECODE_ENABLE_SERIAL_PORT1	BIT(7)
+#define   DECODE_ENABLE_SERIAL_PORT2	BIT(8)
+#define   DECODE_ENABLE_SERIAL_PORT3	BIT(9)
+#define   DECODE_ENABLE_SERIAL_PORT4	BIT(10)
+#define   DECODE_ENABLE_SERIAL_PORT5	BIT(11)
+#define   DECODE_ENABLE_SERIAL_PORT6	BIT(12)
+#define   DECODE_ENABLE_SERIAL_PORT7	BIT(13)
+#define   DECODE_ENABLE_AUDIO_PORT0	BIT(14)
+#define   DECODE_ENABLE_AUDIO_PORT1	BIT(15)
+#define   DECODE_ENABLE_AUDIO_PORT2	BIT(16)
+#define   DECODE_ENABLE_AUDIO_PORT3	BIT(17)
+#define   DECODE_ENABLE_MIDI_PORT0	BIT(18)
+#define   DECODE_ENABLE_MIDI_PORT1	BIT(19)
+#define   DECODE_ENABLE_MIDI_PORT2	BIT(20)
+#define   DECODE_ENABLE_MIDI_PORT3	BIT(21)
+#define   DECODE_ENABLE_MSS_PORT0	BIT(22)
+#define   DECODE_ENABLE_MSS_PORT1	BIT(23)
+#define   DECODE_ENABLE_MSS_PORT2	BIT(24)
+#define   DECODE_ENABLE_MSS_PORT3	BIT(25)
+#define   DECODE_ENABLE_FDC_PORT0	BIT(26)
+#define   DECODE_ENABLE_FDC_PORT1	BIT(27)
+#define   DECODE_ENABLE_GAME_PORT	BIT(28)
+#define   DECODE_ENABLE_KBC_PORT	BIT(29)
+#define   DECODE_ENABLE_ACPIUC_PORT	BIT(30)
+#define   DECODE_ENABLE_ADLIB_PORT	BIT(31)
+
+#define LPC_IO_OR_MEM_DECODE_ENABLE	0x48
+#define   LPC_WIDEIO2_ENABLE		BIT(25)
+#define   LPC_WIDEIO1_ENABLE		BIT(24)
+#define   LPC_WIDEIO0_ENABLE		BIT(2)
+
+#define LPC_WIDEIO_GENERIC_PORT		0x64
+
+#define LPC_ALT_WIDEIO_RANGE_ENABLE	0x74
+#define   LPC_ALT_WIDEIO2_ENABLE	BIT(3)
+#define   LPC_ALT_WIDEIO1_ENABLE	BIT(2)
+#define   LPC_ALT_WIDEIO0_ENABLE	BIT(0)
+
+#define LPC_WIDEIO2_GENERIC_PORT	0x90
+
+#define SPI_CNTRL0 			0x00
+#define   SPI_READ_MODE_MASK		(BIT(30) | BIT(29) | BIT(18))
+/* Nominal is 16.7MHz on older devices, 33MHz on newer */
+#define   SPI_READ_MODE_NOM		0x00000000
+#define   SPI_READ_MODE_DUAL112		(          BIT(29)          )
+#define   SPI_READ_MODE_QUAD114		(          BIT(29) | BIT(18))
+#define   SPI_READ_MODE_DUAL122		(BIT(30)                    )
+#define   SPI_READ_MODE_QUAD144		(BIT(30) |           BIT(18))
+#define   SPI_READ_MODE_NORMAL66	(BIT(30) | BIT(29)          )
+/* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */
+#define   SPI_READ_MODE_FAST_HUDSON1	(                    BIT(18))
+#define   SPI_READ_MODE_FAST		(BIT(30) | BIT(29) | BIT(18))
+#define   SPI_ARB_ENABLE		BIT(19)
+
+#define SPI_CNTRL1			0x0c
+/* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */
+#define   SPI_CNTRL1_SPEED_MASK 	(BIT(15) | BIT(14) | BIT(13) | BIT(12))
+#define   SPI_NORM_SPEED_SH		12
+#define   SPI_FAST_SPEED_SH		8
+
+#define SPI100_ENABLE			0x20
+#define   SPI_USE_SPI100		BIT(0)
+
+#define SPI100_SPEED_CONFIG		0x22
+#define   SPI_SPEED_66M			(0x0)
+#define   SPI_SPEED_33M			(                  BIT(0))
+#define   SPI_SPEED_22M			(         BIT(1)         )
+#define   SPI_SPEED_16M			(         BIT(1) | BIT(0))
+#define   SPI_SPEED_100M		(BIT(2)                  )
+#define   SPI_SPEED_800K		(BIT(2) |          BIT(0))
+#define   SPI_NORM_SPEED_NEW_SH		12
+#define   SPI_FAST_SPEED_NEW_SH		8
+#define   SPI_ALT_SPEED_NEW_SH 		4
+#define   SPI_TPM_SPEED_NEW_SH		0
+
+#define SPI100_HOST_PREF_CONFIG 	0x2c
+#define   SPI_RD4DW_EN_HOST		BIT(15)
+
+static inline int hudson_sata_enable(void)
+{
+	/* True if IDE or AHCI. */
+	return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 2);
+}
+
+static inline int hudson_ide_enable(void)
+{
+	/* True if IDE or LEGACY IDE. */
+	return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3);
+}
+
+void configure_hudson_uart(void);
+void hudson_clk_output_48Mhz(void);
+void hudson_disable_4dw_burst(void);
+void hudson_enable(device_t dev);
+void hudson_final(void *chip_info);
+void hudson_init(void *chip_info);
+void hudson_lpc_port80(void);
+void hudson_lpc_decode(void);
+void hudson_pci_port80(void);
+void hudson_read_mode(u32 mode);
+void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm);
+void hudson_set_readspeed(u16 norm, u16 fast);
+void hudson_tpm_decode_spi(void);
+void lpc_wideio_512_window(uint16_t base);
+void lpc_wideio_16_window(uint16_t base);
+u8 pm_read8(u8 reg);
+u16 pm_read16(u16 reg);
+void pm_write8(u8 reg, u8 value);
+void pm_write16(u8 reg, u16 value);
+int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
+void s3_resume_init_data(void *FchParams);
+int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
+
+#endif /* STONEYRIDGE_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/imc.h b/src/soc/amd/stoneyridge/include/soc/imc.h
new file mode 100644
index 0000000000..3d0e7406c2
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/imc.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef STONEYRIDGE_IMC_H
+#define STONEYRIDGE_IMC_H
+
+#include <Porting.h>
+#include <AGESA.h>
+#include <FchCommonCfg.h>
+
+void imc_reg_init(void);
+void enable_imc_thermal_zone(void);
+void oem_fan_control(FCH_DATA_BLOCK *FchParams);
+
+#endif
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
new file mode 100644
index 0000000000..cfd79d8da1
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _PI_STONEYRIDGE_PCI_DEVS_H_
+#define _PI_STONEYRIDGE_PCI_DEVS_H_
+
+#define BUS0			0
+
+/* XHCI */
+#define XHCI_DEV		0x10
+#define XHCI_FUNC		0
+#define XHCI_DEVID		0x7814
+#define XHCI_DEVFN		PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
+
+#define XHCI2_DEV		0x10
+#define XHCI2_FUNC		1
+#define XHCI2_DEVID		0x7814
+#define XHCI2_DEVFN		PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC)
+
+/* SATA */
+#define SATA_DEV		0x11
+#define SATA_FUNC		0
+#define SATA_IDE_DEVID		0x7800
+#define AHCI_DEVID_MS		0x7801
+#define AHCI_DEVID_AMD		0x7804
+#define SATA_DEVFN		PCI_DEVFN(SATA_DEV,SATA_FUNC)
+
+/* OHCI */
+#define OHCI1_DEV		0x12
+#define OHCI1_FUNC		0
+#define OHCI2_DEV		0x13
+#define OHCI2_FUNC		0
+#define OHCI3_DEV		0x16
+#define OHCI3_FUNC		0
+#define OHCI4_DEV		0x14
+#define OHCI4_FUNC		5
+#define OHCI_DEVID		0x7807
+#define OHCI1_DEVFN		PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC)
+#define OHCI2_DEVFN		PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC)
+#define OHCI3_DEVFN		PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC)
+#define OHCI4_DEVFN		PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC)
+
+/* EHCI */
+#define EHCI1_DEV		0x12
+#define EHCI1_FUNC		2
+#define EHCI2_DEV		0x13
+#define EHCI2_FUNC		2
+#define EHCI3_DEV		0x16
+#define EHCI3_FUNC		2
+#define EHCI_DEVID		0x7808
+#define EHCI1_DEVFN		PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC)
+#define EHCI2_DEVFN		PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC)
+#define EHCI3_DEVFN		PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC)
+
+/* SMBUS */
+#define SMBUS_DEV		0x14
+#define SMBUS_FUNC		0
+#define SMBUS_DEVID		0x780B
+#define SMBUS_DEVFN		PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
+
+/* IDE */
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
+#define IDE_DEV			0x14
+#define IDE_FUNC		1
+#define IDE_DEVID		0x780C
+#define IDE_DEVFN		PCI_DEVFN(IDE_DEV,IDE_FUNC)
+#endif
+
+/* HD Audio */
+#define HDA_DEV			0x14
+#define HDA_FUNC		2
+#define HDA_DEVID		0x780D
+#define HDA_DEVFN		PCI_DEVFN(HDA_DEV,HDA_FUNC)
+
+/* LPC BUS */
+#define PCU_DEV			0x14
+#define LPC_FUNC		3
+#define LPC_DEVID		0x780E
+#define LPC_DEVFN		PCI_DEVFN(LPC_DEV,LPC_FUNC)
+
+/* PCI Ports */
+#define SB_PCI_PORT_DEV		0x14
+#define SB_PCI_PORT_FUNC	4
+#define SB_PCI_PORT_DEVID	0x780F
+#define SB_PCI_PORT_DEVFN	PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC)
+
+/* SD Controller */
+#define SD_DEV			0x14
+#define SD_FUNC			7
+#define SD_DEVID		0x7806
+#define SD_DEVFN		PCI_DEVFN(SD_DEV,SD_FUNC)
+
+/* PCIe Ports */
+#if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
+#define SB_PCIE_DEV		0x15
+#define SB_PCIE_PORT1_FUNC	0
+#define SB_PCIE_PORT2_FUNC	1
+#define SB_PCIE_PORT3_FUNC	2
+#define SB_PCIE_PORT4_FUNC	3
+#define SB_PCIE_PORT1_DEVID	0x7820
+#define SB_PCIE_PORT2_DEVID	0x7821
+#define SB_PCIE_PORT3_DEVID	0x7822
+#define SB_PCIE_PORT4_DEVID	0x7823
+#define SB_PCIE_PORT1_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC)
+#define SB_PCIE_PORT2_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC)
+#define SB_PCIE_PORT3_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC)
+#define SB_PCIE_PORT4_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC)
+#endif
+
+#endif /* _PI_STONEYRIDGE_PCI_DEVS_H_ */
diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h
new file mode 100644
index 0000000000..d4499fced0
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/smbus.h
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef STONEYRIDGE_SMBUS_H
+#define STONEYRIDGE_SMBUS_H
+
+#include <stdint.h>
+
+#define SMBHSTSTAT		0x0
+#define SMBSLVSTAT		0x1
+#define SMBHSTCTRL		0x2
+#define SMBHSTCMD		0x3
+#define SMBHSTADDR		0x4
+#define SMBHSTDAT0		0x5
+#define SMBHSTDAT1		0x6
+#define SMBHSTBLKDAT		0x7
+#define SMBSLVCTRL		0x8
+#define SMBSLVCMD_SHADOW	0x9
+#define SMBSLVEVT		0xa
+#define SMBSLVDAT		0xc
+
+#define AX_INDXC		0
+#define AX_INDXP		2
+#define AXCFG			4
+#define ABCFG			6
+#define RC_INDXC		1
+#define RC_INDXP		3
+
+#define AB_INDX			0xCD8
+#define AB_DATA			(AB_INDX+4)
+
+/* Between 1-10 seconds, We should never timeout normally
+ * Longer than this is just painful when a timeout condition occurs.
+ */
+#define SMBUS_TIMEOUT (100 * 1000 * 10)
+
+#define abcfg_reg(reg, mask, val)	\
+	alink_ab_indx((ABCFG), (reg), (mask), (val))
+#define axcfg_reg(reg, mask, val)	\
+	alink_ab_indx((AXCFG), (reg), (mask), (val))
+#define axindxc_reg(reg, mask, val)	\
+	alink_ax_indx((AX_INDXC), (reg), (mask), (val))
+#define axindxp_reg(reg, mask, val)		\
+	alink_ax_indx((AX_INDXP), (reg), (mask), (val))
+#define rcindxc_reg(reg, port, mask, val)	\
+	alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
+#define rcindxp_reg(reg, port, mask, val)	\
+	alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
+
+int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
+int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
+int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
+int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
+void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
+void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
+void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
+
+#endif	/* STONEYRIDGE_SMBUS_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h
new file mode 100644
index 0000000000..7a3c804452
--- /dev/null
+++ b/src/soc/amd/stoneyridge/include/soc/smi.h
@@ -0,0 +1,65 @@
+/*
+ * Utilities for SMI handlers and SMM setup
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me@gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#ifndef _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H
+#define _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H
+
+#include <arch/io.h>
+
+/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it.
+ * This is defined by AGESA, but we dpn't include AGESA headers to avoid
+ * polluting the namesace.
+ */
+#define SMI_BASE		0xfed80200
+
+#define SMI_REG_SMITRIG0	0x98
+#define SMITRG0_EOS		(1 << 28)
+#define SMITRG0_SMIENB		(1 << 31)
+
+#define SMI_REG_CONTROL0	0xa0
+
+enum smi_mode {
+	SMI_MODE_DISABLE = 0,
+	SMI_MODE_SMI = 1,
+	SMI_MODE_NMI = 2,
+	SMI_MODE_IRQ13 = 3,
+};
+
+enum smi_lvl {
+	SMI_LVL_LOW = 0,
+	SMI_LVL_HIGH = 1,
+};
+
+static inline uint32_t smi_read32(uint8_t offset)
+{
+	return read32((void *)(SMI_BASE + offset));
+}
+
+static inline void smi_write32(uint8_t offset, uint32_t value)
+{
+	write32((void *)(SMI_BASE + offset), value);
+}
+
+static inline uint16_t smi_read16(uint8_t offset)
+{
+	return read16((void *)(SMI_BASE + offset));
+}
+
+static inline void smi_write16(uint8_t offset, uint16_t value)
+{
+	write16((void *)(SMI_BASE + offset), value);
+}
+
+void hudson_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
+void hudson_disable_gevent_smi(uint8_t gevent);
+void hudson_enable_acpi_cmd_smi(void);
+
+#ifndef __SMM__
+void hudson_enable_smi_generation(void);
+#endif
+
+#endif /* _SOUTHBRIDGE_AMD_PI_STONEYRIDGE_SMI_H */