soc/amd/stoneyridge: Fix most checkpatch errors

Correct the majority of reported errors and mark most of the
remaining ones as todo.  (Some of the lines requiring a >80
break are indented too much currently.)  Some of the alignment
in hudson.h still causes checkpatch errors, but this is
intentionally left as-is.

Also make other misc. changes, e.g. consistency in lower-case
for hex values, using defined values, etc.

These changes were confirmed to cause no changes in a Gardenia
build.  No other improvements were made, e.g. changing to helper
functions, or converting functions like __outbyte().

BUG=chrome-os-partner:622407746

Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

6 files changed, 101 insertions, 89 deletions

diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h
index 361c06f5b7..f3f60d3b61 100644
--- a/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h
+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_defs.h
@@ -22,7 +22,7 @@
  * routing table
  */
 
-#define PIRQ_NC		0x1F	/* Not Used */
+#define PIRQ_NC		0x1f	/* Not Used */
 #define PIRQ_A		0x00	/* INT A */
 #define PIRQ_B		0x01	/* INT B */
 #define PIRQ_C		0x02	/* INT C */
@@ -33,12 +33,12 @@
 #define PIRQ_H		0x07	/* INT H */
 #define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings - See FCH Spec */
 #define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
-#define PIRQ_MISC1	0x0A	/* Miscellaneous1 IRQ Settings */
-#define PIRQ_MISC2	0x0B	/* Miscellaneous2 IRQ Settings */
-#define PIRQ_SIRQA	0x0C	/* Serial IRQ INTA */
-#define PIRQ_SIRQB	0x0D	/* Serial IRQ INTB */
-#define PIRQ_SIRQC	0x0E	/* Serial IRQ INTC */
-#define PIRQ_SIRQD	0x0F	/* Serial IRQ INTD */
+#define PIRQ_MISC1	0x0a	/* Miscellaneous1 IRQ Settings */
+#define PIRQ_MISC2	0x0b	/* Miscellaneous2 IRQ Settings */
+#define PIRQ_SIRQA	0x0c	/* Serial IRQ INTA */
+#define PIRQ_SIRQB	0x0d	/* Serial IRQ INTB */
+#define PIRQ_SIRQC	0x0e	/* Serial IRQ INTC */
+#define PIRQ_SIRQD	0x0f	/* Serial IRQ INTD */
 #define PIRQ_SCI	0x10	/* SCI IRQ */
 #define PIRQ_SMBUS	0x11	/* SMBUS	14h.0 */
 #define PIRQ_ASF	0x12	/* ASF */
@@ -46,7 +46,7 @@
 #define PIRQ_FC		0x14	/* FC */
 #define PIRQ_GEC	0x15	/* GEC */
 #define PIRQ_PMON	0x16	/* Performance Monitor */
-#define PIRQ_SD 	0x17	/* SD */
+#define PIRQ_SD		0x17	/* SD */
 #define PIRQ_IMC0	0x20	/* IMC INT0 */
 #define PIRQ_IMC1	0x21	/* IMC INT1 */
 #define PIRQ_IMC2	0x22	/* IMC INT2 */
diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
index 30ab0d4839..ab1f70b869 100644
--- a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
+++ b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h
@@ -16,17 +16,22 @@
 #ifndef AMD_PCI_INT_TYPES_H
 #define AMD_PCI_INT_TYPES_H
 
-const char * intr_types[] = {
-	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
-	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
-	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t", "SD\t\t",
-	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
-	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
-	[0x7F] = "RSVD\t",
+const char *intr_types[] = {
+	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t",
+				"INTF#\t", "INTG#\t", "INTH#\t",
+	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA",
+				"Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
+	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t",
+				"PerMon\t", "SD\t\t",
+	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t",
+				"IMC INT4\t", "IMC INT5\t",
+	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB",
+				"Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
+	[0x7f] = "RSVD\t",
 	[0x40] = "IDE\t", "SATA\t",
 	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t",
 	[0x62] = "GPIO\t",
-	[0x70] = "I2C0\t", "I2C1\t", "I2C2\t","I2C3\t", "UART0\t", "UART1\t",
+	[0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t",
 };
 
 #endif /* AMD_PCI_INT_TYPES_H */
diff --git a/src/soc/amd/stoneyridge/include/soc/gpio.h b/src/soc/amd/stoneyridge/include/soc/gpio.h
index 07d4009efa..a66701ac56 100644
--- a/src/soc/amd/stoneyridge/include/soc/gpio.h
+++ b/src/soc/amd/stoneyridge/include/soc/gpio.h
@@ -30,98 +30,98 @@
 #define   GPIO_0	(GPIO_BANK0_CONTROL + 0x00)
 #define   GPIO_1	(GPIO_BANK0_CONTROL + 0x04)
 #define   GPIO_2	(GPIO_BANK0_CONTROL + 0x08)
-#define   GPIO_3	(GPIO_BANK0_CONTROL + 0x0C)
+#define   GPIO_3	(GPIO_BANK0_CONTROL + 0x0c)
 #define   GPIO_4	(GPIO_BANK0_CONTROL + 0x10)
 #define   GPIO_5	(GPIO_BANK0_CONTROL + 0x14)
 #define   GPIO_6	(GPIO_BANK0_CONTROL + 0x18)
-#define   GPIO_7	(GPIO_BANK0_CONTROL + 0x1C)
+#define   GPIO_7	(GPIO_BANK0_CONTROL + 0x1c)
 #define   GPIO_8	(GPIO_BANK0_CONTROL + 0x20)
 #define   GPIO_9	(GPIO_BANK0_CONTROL + 0x24)
 #define   GPIO_10	(GPIO_BANK0_CONTROL + 0x28)
-#define   GPIO_11	(GPIO_BANK0_CONTROL + 0x2C)
+#define   GPIO_11	(GPIO_BANK0_CONTROL + 0x2c)
 #define   GPIO_12	(GPIO_BANK0_CONTROL + 0x30)
 #define   GPIO_13	(GPIO_BANK0_CONTROL + 0x34)
 #define   GPIO_14	(GPIO_BANK0_CONTROL + 0x38)
-#define   GPIO_15	(GPIO_BANK0_CONTROL + 0x3C)
+#define   GPIO_15	(GPIO_BANK0_CONTROL + 0x3c)
 #define   GPIO_16	(GPIO_BANK0_CONTROL + 0x40)
 #define   GPIO_17	(GPIO_BANK0_CONTROL + 0x44)
 #define   GPIO_18	(GPIO_BANK0_CONTROL + 0x48)
-#define   GPIO_19	(GPIO_BANK0_CONTROL + 0x4C)
+#define   GPIO_19	(GPIO_BANK0_CONTROL + 0x4c)
 #define   GPIO_20	(GPIO_BANK0_CONTROL + 0x50)
 #define   GPIO_21	(GPIO_BANK0_CONTROL + 0x54)
 #define   GPIO_22	(GPIO_BANK0_CONTROL + 0x58)
-#define   GPIO_23	(GPIO_BANK0_CONTROL + 0x5C)
+#define   GPIO_23	(GPIO_BANK0_CONTROL + 0x5c)
 #define   GPIO_24	(GPIO_BANK0_CONTROL + 0x60)
 #define   GPIO_25	(GPIO_BANK0_CONTROL + 0x64)
 #define   GPIO_26	(GPIO_BANK0_CONTROL + 0x68)
-#define   GPIO_39	(GPIO_BANK0_CONTROL + 0x9C)
-#define   GPIO_42	(GPIO_BANK0_CONTROL + 0xA8)
+#define   GPIO_39	(GPIO_BANK0_CONTROL + 0x9c)
+#define   GPIO_42	(GPIO_BANK0_CONTROL + 0xa8)
 
 /* GPIO_64 - GPIO_127 */
 #define GPIO_BANK1 (CONTROL AMD_SB_ACPI_MMIO_ADDR + 0x1600)
 #define   GPIO_64	(GPIO_BANK1_CONTROL + 0x00)
 #define   GPIO_65	(GPIO_BANK1_CONTROL + 0x04)
 #define   GPIO_66	(GPIO_BANK1_CONTROL + 0x08)
-#define   GPIO_67	(GPIO_BANK1_CONTROL + 0x0C)
+#define   GPIO_67	(GPIO_BANK1_CONTROL + 0x0c)
 #define   GPIO_68	(GPIO_BANK1_CONTROL + 0x10)
 #define   GPIO_69	(GPIO_BANK1_CONTROL + 0x14)
 #define   GPIO_70	(GPIO_BANK1_CONTROL + 0x18)
-#define   GPIO_71	(GPIO_BANK1_CONTROL + 0x1C)
+#define   GPIO_71	(GPIO_BANK1_CONTROL + 0x1c)
 #define   GPIO_72	(GPIO_BANK1_CONTROL + 0x20)
 #define   GPIO_74	(GPIO_BANK1_CONTROL + 0x28)
-#define   GPIO_75	(GPIO_BANK1_CONTROL + 0x2C)
+#define   GPIO_75	(GPIO_BANK1_CONTROL + 0x2c)
 #define   GPIO_76	(GPIO_BANK1_CONTROL + 0x30)
 #define   GPIO_84	(GPIO_BANK1_CONTROL + 0x50)
 #define   GPIO_85	(GPIO_BANK1_CONTROL + 0x54)
 #define   GPIO_86	(GPIO_BANK1_CONTROL + 0x58)
-#define   GPIO_87	(GPIO_BANK1_CONTROL + 0x5C)
+#define   GPIO_87	(GPIO_BANK1_CONTROL + 0x5c)
 #define   GPIO_88	(GPIO_BANK1_CONTROL + 0x60)
 #define   GPIO_89	(GPIO_BANK1_CONTROL + 0x64)
 #define   GPIO_90	(GPIO_BANK1_CONTROL + 0x68)
-#define   GPIO_91	(GPIO_BANK1_CONTROL + 0x6C)
+#define   GPIO_91	(GPIO_BANK1_CONTROL + 0x6c)
 #define   GPIO_92	(GPIO_BANK1_CONTROL + 0x70)
 #define   GPIO_93	(GPIO_BANK1_CONTROL + 0x74)
-#define   GPIO_95	(GPIO_BANK1_CONTROL + 0x7C)
+#define   GPIO_95	(GPIO_BANK1_CONTROL + 0x7c)
 #define   GPIO_96	(GPIO_BANK1_CONTROL + 0x80)
 #define   GPIO_97	(GPIO_BANK1_CONTROL + 0x84)
 #define   GPIO_98	(GPIO_BANK1_CONTROL + 0x88)
-#define   GPIO_99	(GPIO_BANK1_CONTROL + 0x8C)
+#define   GPIO_99	(GPIO_BANK1_CONTROL + 0x8c)
 #define   GPIO_100	(GPIO_BANK1_CONTROL + 0x90)
 #define   GPIO_101	(GPIO_BANK1_CONTROL + 0x94)
 #define   GPIO_102	(GPIO_BANK1_CONTROL + 0x98)
-#define   GPIO_113	(GPIO_BANK1_CONTROL + 0xC4)
-#define   GPIO_114	(GPIO_BANK1_CONTROL + 0xC8)
-#define   GPIO_115	(GPIO_BANK1_CONTROL + 0xCC)
-#define   GPIO_116	(GPIO_BANK1_CONTROL + 0xD0)
-#define   GPIO_117	(GPIO_BANK1_CONTROL + 0xD4)
-#define   GPIO_118	(GPIO_BANK1_CONTROL + 0xD8)
-#define   GPIO_119	(GPIO_BANK1_CONTROL + 0xDC)
-#define   GPIO_120	(GPIO_BANK1_CONTROL + 0xE0)
-#define   GPIO_121	(GPIO_BANK1_CONTROL + 0xE4)
-#define   GPIO_122	(GPIO_BANK1_CONTROL + 0xE8)
-#define   GPIO_126	(GPIO_BANK1_CONTROL + 0xF8)
+#define   GPIO_113	(GPIO_BANK1_CONTROL + 0xc4)
+#define   GPIO_114	(GPIO_BANK1_CONTROL + 0xc8)
+#define   GPIO_115	(GPIO_BANK1_CONTROL + 0xcc)
+#define   GPIO_116	(GPIO_BANK1_CONTROL + 0xd0)
+#define   GPIO_117	(GPIO_BANK1_CONTROL + 0xd4)
+#define   GPIO_118	(GPIO_BANK1_CONTROL + 0xd8)
+#define   GPIO_119	(GPIO_BANK1_CONTROL + 0xdc)
+#define   GPIO_120	(GPIO_BANK1_CONTROL + 0xe0)
+#define   GPIO_121	(GPIO_BANK1_CONTROL + 0xe4)
+#define   GPIO_122	(GPIO_BANK1_CONTROL + 0xe8)
+#define   GPIO_126	(GPIO_BANK1_CONTROL + 0xf8)
 
 /* GPIO_128 - GPIO_183 */
 #define GPIO_BANK2_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x1700)
 #define   GPIO_129	(GPIO_BANK2_CONTROL + 0x04)
 #define   GPIO_130	(GPIO_BANK2_CONTROL + 0x08)
-#define   GPIO_131	(GPIO_BANK2_CONTROL + 0x0C)
+#define   GPIO_131	(GPIO_BANK2_CONTROL + 0x0c)
 #define   GPIO_132	(GPIO_BANK2_CONTROL + 0x10)
 #define   GPIO_133	(GPIO_BANK2_CONTROL + 0x14)
 #define   GPIO_134	(GPIO_BANK2_CONTROL + 0x18)
-#define   GPIO_135	(GPIO_BANK2_CONTROL + 0x1C)
+#define   GPIO_135	(GPIO_BANK2_CONTROL + 0x1c)
 #define   GPIO_136	(GPIO_BANK2_CONTROL + 0x20)
 #define   GPIO_137	(GPIO_BANK2_CONTROL + 0x24)
 #define   GPIO_138	(GPIO_BANK2_CONTROL + 0x28)
-#define   GPIO_139	(GPIO_BANK2_CONTROL + 0x2C)
+#define   GPIO_139	(GPIO_BANK2_CONTROL + 0x2c)
 #define   GPIO_140	(GPIO_BANK2_CONTROL + 0x30)
 #define   GPIO_141	(GPIO_BANK2_CONTROL + 0x34)
 #define   GPIO_142	(GPIO_BANK2_CONTROL + 0x38)
-#define   GPIO_143	(GPIO_BANK2_CONTROL + 0x3C)
+#define   GPIO_143	(GPIO_BANK2_CONTROL + 0x3c)
 #define   GPIO_144	(GPIO_BANK2_CONTROL + 0x40)
 #define   GPIO_145	(GPIO_BANK2_CONTROL + 0x44)
 #define   GPIO_146	(GPIO_BANK2_CONTROL + 0x48)
-#define   GPIO_147	(GPIO_BANK2_CONTROL + 0x4C)
+#define   GPIO_147	(GPIO_BANK2_CONTROL + 0x4c)
 #define   GPIO_148	(GPIO_BANK2_CONTROL + 0x50)
 
 typedef uint32_t gpio_t;
diff --git a/src/soc/amd/stoneyridge/include/soc/hudson.h b/src/soc/amd/stoneyridge/include/soc/hudson.h
index bfe506edd1..c69ab679e6 100644
--- a/src/soc/amd/stoneyridge/include/soc/hudson.h
+++ b/src/soc/amd/stoneyridge/include/soc/hudson.h
@@ -29,6 +29,9 @@
  */
 #define PM_MMIO_BASE			0xfed80300
 
+#define APU_UART0_BASE			0xfedc6000
+#define APU_UART1_BASE			0xfedc8000
+
 /* Power management index/data registers */
 #define BIOSRAM_INDEX			0xcd4
 #define BIOSRAM_DATA			0xcd5
@@ -44,15 +47,17 @@
 #define PM_TMR_BLK			0x64
 #define PM_CPU_CTRL			0x66
 #define PM_GPE0_BLK			0x68
-#define PM_ACPI_SMI_CMD			0x6A
+#define PM_ACPI_SMI_CMD			0x6a
 #define PM_ACPI_CONF			0x74
-#define PM_PMIO_DEBUG			0xD2
-#define PM_MANUAL_RESET			0xD3
-#define PM_HUD_SD_FLASH_CTRL		0xE7
-#define PM_YANG_SD_FLASH_CTRL		0xE8
-#define PM_PCIB_CFG			0xEA
+#define PM_PMIO_DEBUG			0xd2
+#define PM_MANUAL_RESET			0xd3
+#define PM_HUD_SD_FLASH_CTRL		0xe7
+#define PM_YANG_SD_FLASH_CTRL		0xe8
+#define PM_PCIB_CFG			0xea
+
+#define SYS_RESET			0xcf9
 
-#define STONEYRIDGE_ACPI_IO_BASE		CONFIG_STONEYRIDGE_ACPI_IO_BASE
+#define STONEYRIDGE_ACPI_IO_BASE	CONFIG_STONEYRIDGE_ACPI_IO_BASE
 #define ACPI_PM_EVT_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x00) /* 4 bytes */
 #define ACPI_PM1_CNT_BLK	(STONEYRIDGE_ACPI_IO_BASE + 0x04) /* 2 bytes */
 #define ACPI_PM_TMR_BLK		(STONEYRIDGE_ACPI_IO_BASE + 0x18) /* 4 bytes */
@@ -69,10 +74,10 @@
 #define REV_STONEYRIDGE_A11			0x11
 #define REV_STONEYRIDGE_A12			0x12
 
-#define SPIROM_BASE_ADDRESS_REGISTER	0xA0
+#define SPIROM_BASE_ADDRESS_REGISTER	0xa0
 #define   ROUTE_TPM_2_SPI		BIT(3)
 #define   SPI_ROM_ENABLE		0x02
-#define   SPI_BASE_ADDRESS		0xFEC10000
+#define   SPI_BASE_ADDRESS		0xfec10000
 
 #define LPC_IO_PORT_DECODE_ENABLE	0x44
 #define   DECODE_ENABLE_PARALLEL_PORT0	BIT(0)
@@ -122,7 +127,7 @@
 
 #define LPC_WIDEIO2_GENERIC_PORT	0x90
 
-#define SPI_CNTRL0 			0x00
+#define SPI_CNTRL0			0x00
 #define   SPI_READ_MODE_MASK		(BIT(30) | BIT(29) | BIT(18))
 /* Nominal is 16.7MHz on older devices, 33MHz on newer */
 #define   SPI_READ_MODE_NOM		0x00000000
@@ -138,7 +143,7 @@
 
 #define SPI_CNTRL1			0x0c
 /* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */
-#define   SPI_CNTRL1_SPEED_MASK 	(BIT(15) | BIT(14) | BIT(13) | BIT(12))
+#define   SPI_CNTRL1_SPEED_MASK		(BIT(15) | BIT(14) | BIT(13) | BIT(12))
 #define   SPI_NORM_SPEED_SH		12
 #define   SPI_FAST_SPEED_SH		8
 
@@ -154,22 +159,24 @@
 #define   SPI_SPEED_800K		(BIT(2) |          BIT(0))
 #define   SPI_NORM_SPEED_NEW_SH		12
 #define   SPI_FAST_SPEED_NEW_SH		8
-#define   SPI_ALT_SPEED_NEW_SH 		4
+#define   SPI_ALT_SPEED_NEW_SH		4
 #define   SPI_TPM_SPEED_NEW_SH		0
 
-#define SPI100_HOST_PREF_CONFIG 	0x2c
+#define SPI100_HOST_PREF_CONFIG		0x2c
 #define   SPI_RD4DW_EN_HOST		BIT(15)
 
 static inline int hudson_sata_enable(void)
 {
 	/* True if IDE or AHCI. */
-	return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 2);
+	return (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||
+					(CONFIG_STONEYRIDGE_SATA_MODE == 2);
 }
 
 static inline int hudson_ide_enable(void)
 {
 	/* True if IDE or LEGACY IDE. */
-	return (CONFIG_STONEYRIDGE_SATA_MODE == 0) || (CONFIG_STONEYRIDGE_SATA_MODE == 3);
+	return (CONFIG_STONEYRIDGE_SATA_MODE == 0) ||
+					(CONFIG_STONEYRIDGE_SATA_MODE == 3);
 }
 
 void configure_hudson_uart(void);
diff --git a/src/soc/amd/stoneyridge/include/soc/pci_devs.h b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
index cfd79d8da1..f0445422a9 100644
--- a/src/soc/amd/stoneyridge/include/soc/pci_devs.h
+++ b/src/soc/amd/stoneyridge/include/soc/pci_devs.h
@@ -22,12 +22,12 @@
 #define XHCI_DEV		0x10
 #define XHCI_FUNC		0
 #define XHCI_DEVID		0x7814
-#define XHCI_DEVFN		PCI_DEVFN(XHCI_DEV,XHCI_FUNC)
+#define XHCI_DEVFN		PCI_DEVFN(XHCI_DEV, XHCI_FUNC)
 
 #define XHCI2_DEV		0x10
 #define XHCI2_FUNC		1
 #define XHCI2_DEVID		0x7814
-#define XHCI2_DEVFN		PCI_DEVFN(XHCI2_DEV,XHCI2_FUNC)
+#define XHCI2_DEVFN		PCI_DEVFN(XHCI2_DEV, XHCI2_FUNC)
 
 /* SATA */
 #define SATA_DEV		0x11
@@ -35,7 +35,7 @@
 #define SATA_IDE_DEVID		0x7800
 #define AHCI_DEVID_MS		0x7801
 #define AHCI_DEVID_AMD		0x7804
-#define SATA_DEVFN		PCI_DEVFN(SATA_DEV,SATA_FUNC)
+#define SATA_DEVFN		PCI_DEVFN(SATA_DEV, SATA_FUNC)
 
 /* OHCI */
 #define OHCI1_DEV		0x12
@@ -47,10 +47,10 @@
 #define OHCI4_DEV		0x14
 #define OHCI4_FUNC		5
 #define OHCI_DEVID		0x7807
-#define OHCI1_DEVFN		PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC)
-#define OHCI2_DEVFN		PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC)
-#define OHCI3_DEVFN		PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC)
-#define OHCI4_DEVFN		PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC)
+#define OHCI1_DEVFN		PCI_DEVFN(OHCI1_DEV, OHCI1_FUNC)
+#define OHCI2_DEVFN		PCI_DEVFN(OHCI2_DEV, OHCI2_FUNC)
+#define OHCI3_DEVFN		PCI_DEVFN(OHCI3_DEV, OHCI3_FUNC)
+#define OHCI4_DEVFN		PCI_DEVFN(OHCI4_DEV, OHCI4_FUNC)
 
 /* EHCI */
 #define EHCI1_DEV		0x12
@@ -60,47 +60,47 @@
 #define EHCI3_DEV		0x16
 #define EHCI3_FUNC		2
 #define EHCI_DEVID		0x7808
-#define EHCI1_DEVFN		PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC)
-#define EHCI2_DEVFN		PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC)
-#define EHCI3_DEVFN		PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC)
+#define EHCI1_DEVFN		PCI_DEVFN(EHCI1_DEV, EHCI1_FUNC)
+#define EHCI2_DEVFN		PCI_DEVFN(EHCI2_DEV, EHCI2_FUNC)
+#define EHCI3_DEVFN		PCI_DEVFN(EHCI3_DEV, EHCI3_FUNC)
 
 /* SMBUS */
 #define SMBUS_DEV		0x14
 #define SMBUS_FUNC		0
-#define SMBUS_DEVID		0x780B
-#define SMBUS_DEVFN		PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC)
+#define SMBUS_DEVID		0x780b
+#define SMBUS_DEVFN		PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC)
 
 /* IDE */
 #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
 #define IDE_DEV			0x14
 #define IDE_FUNC		1
-#define IDE_DEVID		0x780C
-#define IDE_DEVFN		PCI_DEVFN(IDE_DEV,IDE_FUNC)
+#define IDE_DEVID		0x780c
+#define IDE_DEVFN		PCI_DEVFN(IDE_DEV, IDE_FUNC)
 #endif
 
 /* HD Audio */
 #define HDA_DEV			0x14
 #define HDA_FUNC		2
-#define HDA_DEVID		0x780D
-#define HDA_DEVFN		PCI_DEVFN(HDA_DEV,HDA_FUNC)
+#define HDA_DEVID		0x780d
+#define HDA_DEVFN		PCI_DEVFN(HDA_DEV, HDA_FUNC)
 
 /* LPC BUS */
 #define PCU_DEV			0x14
 #define LPC_FUNC		3
-#define LPC_DEVID		0x780E
-#define LPC_DEVFN		PCI_DEVFN(LPC_DEV,LPC_FUNC)
+#define LPC_DEVID		0x780e
+#define LPC_DEVFN		PCI_DEVFN(LPC_DEV, LPC_FUNC)
 
 /* PCI Ports */
 #define SB_PCI_PORT_DEV		0x14
 #define SB_PCI_PORT_FUNC	4
-#define SB_PCI_PORT_DEVID	0x780F
-#define SB_PCI_PORT_DEVFN	PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC)
+#define SB_PCI_PORT_DEVID	0x780f
+#define SB_PCI_PORT_DEVFN	PCI_DEVFN(SB_PCI_PORT_DEV, SB_PCI_PORT_FUNC)
 
 /* SD Controller */
 #define SD_DEV			0x14
 #define SD_FUNC			7
 #define SD_DEVID		0x7806
-#define SD_DEVFN		PCI_DEVFN(SD_DEV,SD_FUNC)
+#define SD_DEVFN		PCI_DEVFN(SD_DEV, SD_FUNC)
 
 /* PCIe Ports */
 #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_PI_BOLTON)
@@ -113,10 +113,10 @@
 #define SB_PCIE_PORT2_DEVID	0x7821
 #define SB_PCIE_PORT3_DEVID	0x7822
 #define SB_PCIE_PORT4_DEVID	0x7823
-#define SB_PCIE_PORT1_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC)
-#define SB_PCIE_PORT2_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC)
-#define SB_PCIE_PORT3_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC)
-#define SB_PCIE_PORT4_DEVFN	PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC)
+#define SB_PCIE_PORT1_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT1_FUNC)
+#define SB_PCIE_PORT2_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT2_FUNC)
+#define SB_PCIE_PORT3_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT3_FUNC)
+#define SB_PCIE_PORT4_DEVFN	PCI_DEVFN(SB_PCIE_DEV, SB_PCIE_PORT4_FUNC)
 #endif
 
 #endif /* _PI_STONEYRIDGE_PCI_DEVS_H_ */
diff --git a/src/soc/amd/stoneyridge/include/soc/smbus.h b/src/soc/amd/stoneyridge/include/soc/smbus.h
index d4499fced0..c9b19e5fc2 100644
--- a/src/soc/amd/stoneyridge/include/soc/smbus.h
+++ b/src/soc/amd/stoneyridge/include/soc/smbus.h
@@ -38,7 +38,7 @@
 #define RC_INDXC		1
 #define RC_INDXP		3
 
-#define AB_INDX			0xCD8
+#define AB_INDX			0xcd8
 #define AB_DATA			(AB_INDX+4)
 
 /* Between 1-10 seconds, We should never timeout normally
@@ -65,6 +65,6 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
 int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
 void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
 void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
+void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val);
 
 #endif	/* STONEYRIDGE_SMBUS_H */