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2021-11-02soc/amd/common/block/cpu: Add support for cbfs_cache regionRaul E Rangel
This change adds the cbfs_cache region into the x86 memlayout. The SoC or mainboard can decide how big the region should be by specifying CBFS_CACHE_SIZE. BUG=b:179699789 TEST=Build guybrush and verify cbfs_cache region wasn't added. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I268b6bc10906932ee94f795684a28cfac247a68c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-02psp_verstage: convert relative address in EFS2Kangheui Won
Addresses in AMD fw table with EFS gen2 are relative addresses, but PSP doesn't accept relative addresses in update_psp_bios_dir(). Check for EFS gen2 and convert them as needed. BUG=b:194263115 TEST=build and boot on guybrush and shuboz Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I95813beba7278480e6640599fcf7445923259361 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-02lib: Add new argument as `ddr_type` to smbios_bus_width_to_spd_width()Subrata Banik
Add DDR5 and LPDDR5 memory type checks while calculating bus width extension (in bits). Additionally, update all caller functions of smbios_bus_width_to_spd_width() to pass `MemoryType` as argument. Update `test_smbios_bus_width_to_spd_width()` to accommodate different memory types. Create new macro to fix incorrect bus width reporting on platform with DDR5 and LPDDR5 memory. With this code changes, on DDR5 system with 2 Ch per DIMM, 32 bit primary bus width per Ch showed the Total width as: Handle 0x000F, DMI type 17, 40 bytes Memory Device Array Handle: 0x0009 Error Information Handle: Not Provided Total Width: 80 bits Data Width: 64 bits Size: 16 GB ... BUG=b:194659789 Tested=On Alder Lake DDR5 RVP, SMBIOS type 17 shows expected `Total Width`. Change-Id: I79ec64c9d522a34cb44b3f575725571823048380 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58601 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-01amd/lpc: Remove the weak functionZheng Bao
BUG=b:140165023 Change-Id: Idb4613dc08c8dee6c92b4dabb39c2f5c189471aa Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-27soc/amd/common/block/graphics: add missing GPU PCI IDsFelix Held
Since the iGPU PCI device IDs for AMD Renoir (family 17h, model 60h) and Lucienne (family 17h, model 68h) are already defined in pci_ids.h, also add them to the pci_device_ids list in the common AMD graphics support block. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1c554d21eece182ecea7b09b45b7aa8a733425d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-10-25soc/amd/common/block/lpc/Makefile: simplify handling spi_dma.cFelix Held
Use the verstage_x86 class for the spi_dma.c target instead of using the verstage class and guarding it with !VBOOT_STARTS_BEFORE_BOOTBLOCK. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b8cafd1ef17df8c485f6594bc0928cea88e436b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-22cpu/x86/mp_init: use cb_err as status return type in remaining functionsFelix Held
Using cb_err as return type of mp_run_on_aps, mp_run_on_all_aps, mp_run_on_all_cpus and mp_park_aps clarifies the meaning of the different return values. This patch also adds the types.h include that provides the definition of the cb_err enum and checks the return value of all 4 functions listed above against the enum values instead of either checking if it's non-zero or less than zero to handle the error case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4b3f03415a041d3ec9cd0e102980e53868b004b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58494 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-21soc/amd/common/block/cpu/smm/finalize: simplify finalize_coresFelix Held
The local variable int r isn't needed, so remove it. This is a preparation to change the return type of mp_run_on_all_cpus from int to enum cb_err which will be done in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie4c454cbfcc581be41ea3463ea6f852a72886128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-20soc/amd/common/block/cpu: Remove magic number in memlayoutRaul E Rangel
The SPI DMA controller can only perform transactions on a cache line boundary. This change removes the magic number and uses the #define to make it clear. BUG=b:179699789 TEST=Boot guybrush to OS Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie7b851dc2433e44a23224c3ff733fdea5fbcca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-10-20psp_verstage: remove psp_ef_table structKangheui Won
psp_efs.h now has embedded_firmware struct which is copied from amdfwtool. Remove psp_ef_table from psp_verstage and use it instead to remove duplicates. TEST=boot on zork and guybrush Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: Ia362445cb7fc565b2d963f264461d833dc0338d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-19soc/amd/common/block/include/psp_efs: don't typedef structFelix Held
Don't use a typedef for the embedded_firmware struct so that it's clearer that this is a struct. TEST=Timeless build for google/guybrush results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I97a02c350af57c8f58014aaf7dda8b4796905ff3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58420 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-19soc/amd/common/block/include/psp_efs: rename embedded_firmware elementsFelix Held
The element at offset 0x14 in the embedded_firmware struct is the pointer to the combo PSP directory header, so rename it from comboable to combo_psp_directory to clarify that this is not a flag, but a pointer to a data structure. Also rename psp_entry to psp_directory since it points to the PSP directory table. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia70e97f10f4fa0ac63cc65a33ecdc956538482b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58418 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-10-18ACPI: Have common acpi_fill_mcfg()Kyösti Mälkki
As long as there is only one PCI segment we do not need more complicated MCFG generation. Change-Id: Ic2a8e84383883039bb7f994227e2e425366f9e13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-10-15soc/amd/common: move configure_espi_with_mb_hook implementationFelix Held
Move the actual implementation of configure_espi_with_mb_hook out of the header file and into the espi_util.c file. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1106e69a52bf329a41e8e12fd09db846310b102a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58340 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd: make configure_espi_with_mb_hook call conditionalFelix Held
If a system doesn't use eSPI or has the eSPI interface already configured in verstage on PSP, not calling configure_espi_with_mb_hook from fch_pre_init makes it a bit more obvious that the eSPI interface initialization will be skipped. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia77b83d56a5dab1bac6cfbbd92d33aa60a9e8b89 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58339 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/common/include/espi: rename configure_espiFelix Held
Rename configure_espi to configure_espi_with_mb_hook to clarify that this function will call into the mb_set_up_early_espi function in the mainboard-specific code if it exists. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5d0f099288b0100242629c736dd69a8add977b5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58338 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-15soc/amd/common/block/i2c: implement proper read_resourceFelix Held
Before this patch the reservation of the MMIO region of the I2C controllers was done in the LPC controller PCI device despite the I2C controllers already being devices in the devicetree. This patch implements this functionality as read_resources function of the I2C device instead. This will only reserve the memory when the I2C devices are enabled in devicetree which is a change from the previous behavior. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I67c853df3be2f593ecfa113ae2f74e5df7cf74e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58307 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-15soc/amd/common/block/lpc: simplify eSPI part of MakefileFelix Held
Since espi_util.c is also built in the case of verstage on PSP, we can just add it to all stages. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I65e07c356aac73c5de2d9ce5582434872a223c19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-14soc/amd/common/acpi/upep: Add Low Power State Entry NotificationsKarthikeyan Ramasubramanian
Add support to handle S0ix entry and exit notifications by adding the corresponding _DSM functions. The function indices are chosen based on the Modern Standby BIOS Implementation Guide 56358 Rev. 1.04. Inside the notification functions perform any mainboard specific S0ix entry and exit actions. BUG=b:195748540 TEST=Build and boot to OS in Guybrush. Ensure that the notification functions are invoked on S0ix entry and exit. Perform suspend/resume cycles for multiple iterations. Change-Id: I3014551f6e281d466628559453a0141a3dd6abad Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58274 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-13soc/amd/common/block/spi: Support fast speed overrideKarthikeyan Ramasubramanian
Add support to override SPI ROM fast speed based on board version. This will allow boards to start at lower speeds during bringup and then switch to higher speeds after assessing the signal integrity. Also implement a default no-op override. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ia8ff3b3bdb53fee142527ae63aa7785945909304 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common: Add support to read and set SPI speeds from verstageKarthikeyan Ramasubramanian
Currently all SPI speed configurations are done through EFS at build time. There is a need to apply SPI speed overrides at run-time - eg. based on board version after assessing the signal integrity. This override configuration can be carried out by PSP verstage and bootblock. Export the APIs to set and read SPI speeds from both PSP verstage and bootblock. BUG=None TEST=Build and boot to OS in guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I281531e506b56173471b918c746f58d1ad97162c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-13soc/amd/common/block/espi_util: Refactor eSPI SetupKarthikeyan Ramasubramanian
eSPI is setup in two different locations in bootblock depending on early port80 routing configuration. Also eSPI is setup in PSP, if verified boot starts before bootblock. Consolidate all the scenarios by initializating eSPI very early in fch_pre_init if verified boot starts after bootblock and eSPI is enabled. BUG=None TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm reset and suspend/resume cycles for 50 iterations each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-12soc/amd/common/block/include/psp_efs: use unsigned type for bitfieldFelix Held
For 1 bit long bit fields an unsigned type should be used. In this case uint32_t is used instead of a generic unsigned int for both consistency reasons with the rest of the file and to clarify that the bits will be packed into a 32 bit memory location. TEST=Resulting image of a timeless build for google/guybrush results in identical binary. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic630d1709174d90336746bc37da504437c12643c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-10-11soc/amd/common/include/lpc: add definitions for LPC LDRQ control bitsFelix Held
The definitions of bit 9 and 10 somehow got swapped between Picasso and Renoir/Cezanne, so put those in the Cezanne-specific header file. The reference code writes the same values to the raw bits in both, so we probably would still get away with putting this into the common header, but it's better to keep the defines consistent with the documentation in all cases. Register and bit definitions are from the Cezanne PPR #56569 Rev 3.03 and cross-checked to be compatible with the Picasso PPR #55570 Rev 3.16. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3a033d63eeb06eed6783e4c3797ad8dea490db8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/55294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-27soc/amd/common/psp_verstage: Introduce boot device driverKarthikeyan Ramasubramanian
PSP verstage can access the boot device either in Programmed I/O mode or DMA mode. Introduce a boot device driver and use the appropriate mode based on the SoC support. BUG=b:194990811 TEST=Build and boot to OS in Guybrush. Change-Id: I8ca5290156199548916852e48f4e11de7cb886fb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57563 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-27soc/amd/common/block/include/acpimmio_map: add AOAC acronym in commentFelix Held
The Always On Always Connected block is referenced as AOAC in the code, so add that acronym in the comment and change the "Connect" to "Connected". Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6a23e0ccff62c6ceddae70e1bef5c5abf872c495 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24soc/amd/common: factor out FSP-related parts of common KconfigFelix Held
TEST=Timeless build for Mandolin results in identical image. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib2fb6c29b9f42c00f252994ae2a40b7ff668105a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57885 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24soc/amd/common: move block/pi out of the block folderFelix Held
Since the binaryPI glue code is specific to a binary interface, but not for a hardware block, move it out of the common blocks directory. This also brings the binaryPI support in line with the FSP support which is used on the newer generations. This also drops the SOC_AMD_COMMON_BLOCK_PI Kconfig option and makes use of the already existing SOC_AMD_PI Kconfig option instead. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I014e538f2772938031950475e456cc40dd05d74c Reviewed-on: https://review.coreboot.org/c/coreboot/+/57884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-24soc/amd/common/block: move binaryPI S3 block into PI blockFelix Held
The code in soc/amd/common/block/s3 is specific to the AMD binaryPI coreboot integration, so move the code to soc/amd/common/block/pi. This drops the SOC_AMD_COMMON_BLOCK_S3 Kconfig option and integrates the dependencies and selections into the SOC_AMD_COMMON_BLOCK_PI Kconfig option. Since only selecting SOC_AMD_COMMON_BLOCK_PI but not SOC_AMD_COMMON_BLOCK_S3 resulted in missing functions in the linking process, we don't lose support for any working configuration by only having one Kconfig option for both parts. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib2bd99a88d8b05216688bc45d9c4f23a007ce870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd/common/blocks/include: rename gpio_banks.h to gpio.hFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie2dbec81dfe503869beb2872b01a7475e2b88b33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57842 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd/common/blocks: rename gpio_banks folder to gpioFelix Held
This brings the AMD SoC GPIO code in line with the Intel SoC code and removes the not really needed suffix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3dfcca2f126eb49c962b5cc32cbcf72e04f3f170 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd: rename program_gpios to gpio_configure_padsFelix Held
Use the same function name as in soc/intel for this functionality. This also brings the function name more in line with the extended version of this function gpio_configure_pads_with_override which additionally supports passing a GPIO override configuration. This might cause some pain for out-of-tree boards, but at some point this should be made more consistent, so I don't see a too strong reason not to do this. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I88852e040f79861ce7d190bf2203f9e0ce156690 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-23soc/amd,intel/common/include/gpio: improve documentation of overridesFelix Held
Explicitly point out that gpio_configure_pads_with_override will ignore GPIOs that are only in the override configuration, but not in the base configuration. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1bdfcac89b81fef773938133a2699897c6ee9415 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-09-22soc/amd/common/block/gpio_banks: Rework GPIO pad configurationFelix Held
Before this patch, gpio_configure_pads_with_override called program_gpios once for each GPIO that needed to be configured which resulted in base_num_pads - 1 unneeded master_switch_set/ master_switch_clr sequences for the gpio_configure_pads_with_override call. Instead implement gpio_configure_pads_with_override as the more generic function and program_gpios as a special case of that which passes an empty override configuration and override pad number to gpio_configure_pads_with_override. TEST=GPIO configuration and multiplexer register values are the same for all GPIOs on google/guybrush right before jumping to the payload before and after the patch. Change-Id: Ia8e47b2a278a1887db5406c1f863ddafa6a68675 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43050 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-21soc/amd/common/block/gpio_banks: add missing types.h includeFelix Held
In this file bool, uint8_t and uint32_t are used, so include types.h directly to have those types defined instead of relying to have those included indirectly via amdblocks/gpio_banks.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6f4626a50219fab818e8bc5087961a731b44e71b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-17soc/amd/common/block/pi/image: replace stdbool.h include with types.hFelix Held
Apart from the bool type, uint8_t, uint32_t and uint64_t are used in this file, so include types.h instead of stdbool.h. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I30088d68132058f40b974fbaa822f322b58ed6c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57723 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-16soc/amd/common/block/pi: Add missing include stdbool.hRaul E Rangel
BUG=b:179699789 TEST=build morphius Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I298ce1ee436a5c8eb8375dc5fe55665bbf977463 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-16drivers/intel/fsp2_0: Pass orientation to fsp_report_framebuffer_infoTim Wawrzynczak
Instead of always passing LB_FB_ORIENTATION_NORMAL, allow the chipsets implementing the callback to pass in an orientation. BUG=b:194967458 BRANCH=dedede Change-Id: I4aacab9449930a75aca9d68bf30d019f86035405 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-09-13soc/amd/common/block/cpu: Add missing includeRaul E Rangel
We use cpuid_eax to get the cpuid family. BUG=b:179699789 TEST=build guybrush Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib73e66241bb0cfd99a035c217c527338aa2d0e4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/57566 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-09Revert "soc/amd/common: Skip psp_verstage on S0i3 resume"Karthikeyan Ramasubramanian
This reverts commit b90e6fdd25f7fcc9db6be50a0b117a7509c6fdb1. Latest releases of PSP does not load PSP verstage on S0i3 resume. Hence no need to skip PSP verstage on S0i3 resume. BUG=b:196400450 TEST=Build and boot to OS in Guybrush. Trigger a suspend/resume cycle and then a reboot and ensure that the system boots to OS. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Iaeb92edb69662e6c06f4d0e3d7b760d4597bf650 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57506 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-09-09soc/amd/common/block/acpi/gpio: add warning for remote GPIO usageFelix Held
Right now the ACPI code doesn't support accessing the remote GPIO block yet, so don't generate invalid remote GPIO access functions and warn about those being unsupported. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id364a59c9650bf4e3633b494b01ab23c0bbc50b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56817 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-09-09soc/amd/common/block/gpio_banks: add remote GPIO supportFelix Held
Some AMD SoCs have a 5th GPIO bank, the remote GPIO bank, which isn't located right after the 4th GPIO bank, but instead at a different location inside the APCIMMIO region. A difference to the first 4 GPIO banks is that the corresponding GPIO MUX registers aren't in a separate bank, but at the end of the remote GPIO region. So this remote GPIO region only supports 48 GPIOs with a 32 bit configuration register each and has the 8 bit GPIO MUX registers beginning at offset 0xc0 in the remote GPIO region. For now using the remote GPIOs from verstage on PSP isn't supported. To support this, it would need to map acpimmio_remote_gpio and update the pointer like it already does for acpimmio_gpio0, acpimmio_iomux and a few others. BUG=b:194524995 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic8d7ff677a99381a5558782b80b0c4cae67602db Reviewed-on: https://review.coreboot.org/c/coreboot/+/56810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-09soc/amd/common/block/acpimmio: add remote GPIO bank ACPIMMIO regionFelix Held
Currently coreboot for the AMD SOCs only supports accessing the up to 4 main GPIO banks of up to 64 GPIOs each. Some AMD SoCs including Cezanne have another GPIO bank in the ACPIMMIO region that can contain up to 48 GPIOs beginning with GPIO 256 which is called the remote GPIO bank. The first 48 DWORDs of that ACPIMMIO bank are the 32 bit wide GPIO registers and beginning at offset 0xc0 it has the corresponding 8 bit wide GPIO MUX registers. BUG=b:194524995 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ice4e3358de17ac2601621814978cdb70e6f2c926 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-09soc/amd/common/block/include/i2c: introduce I2C_RESET_SCL_PIN macroFelix Held
Add and use the I2C_RESET_SCL_PIN macro for populating the i2c_scl_pins array that is used for the sb_reset_i2c_peripherals call to bring the I2C buses into a defined state. TEST=Timeless build results in identical image for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ifedc09d0bf745545fa0510df7d5037f02b9012a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57479 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-08cpu/x86/tsc: Deduplicate Makefile logicAngel Pons
The code under `cpu/x86/tsc` is only compiled in when its `Makefile.inc` is included from platform (CPU/SoC) code and the `UDELAY_TSC` Kconfig option is enabled. Include `cpu/x86/tsc/Makefile.inc` once from `cpu/x86/Makefile.inc` and drop the now-redundant inclusions from platform code. Also, deduplicate the `UDELAY_TSC` guards. Change-Id: I41e96026f37f19de954fd5985b92a08cb97876c1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57456 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08soc/amd/common/block/gpio_banks: add comment about acpimmio_* symbolsFelix Held
Suggested-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I0016a6c7d6581cb261cab6178268c1a86b89c839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56831 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08soc/amd/common/block/gpio_banks: inline iomux_read8 and iomux_write8Felix Held
Since both functions are only called from one function each, inline them into those functions. Also get_gpio_mux just returned the return value of iomux_read8, so there were two functions with identical functionality which shouldn't be the case. Suggested-by: Martin Roth <martinroth@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5662d0226edb25a9954fa47b42e208729a79e5a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56830 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-08soc/amd/common/block/gpio_banks: factor out gpio_mux_ptrFelix Held
This aligns the GPIO MUX access more with the GPIO control register access and will facilitate adding support for the remote GPIO bank. Also change the GPIO number argument type to gpio_t. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I4054656c5cc23ea942e8dd370fbbffca304755d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56787 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08soc/amd/common/include/acpimmio: reduce visibility of GPIO MMIO accessFelix Held
Introduce amdblocks/acpimmio_legacy_gpio100.h so that the old pre-SoC chipsets can still access the raw GPIO100 and IOMUX ACPIMMIO registers while only allowing GPIO accesses through the GPIO API on the SoCs. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I18872dfa40d53ba8b0d7802eec52ede5e2ae617a Reviewed-on: https://review.coreboot.org/c/coreboot/+/56786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08soc/amd/common/block/gpio_banks: move GPIO MUX access functionsFelix Held
Move those two functions near the top of the file to have all functions that do the hardware accesses in one place. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If787e6e1d124a932beafd73e5ce7d0ce4869e800 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-08soc/amd/common/block/gpio_banks/gpio: use unsigned types where neededFelix Held
Use unsigned integers for variables that aren't supposed to become negative. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5ee037221b9818b0474fe0376323e522c1b3b516 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-09-08soc/amd/common/block/gpio_banks/gpio: use gpio_t for GPIO numbersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7cf9cbd2a287dcfe3a47a8a6b164c2b3d8ae95d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56700 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08soc/amd/common: move GPIO ACPIMMIO access functions to gpio_banks blockFelix Held
Since the raw GPIO MMIO register access is now only used inside the gpio_banks block, the gpio_read32 and gpio_write32 functions can be moved to that block to reduce the visibility and enforce the usage of the functions provided by the gpio_banks block. The iomux_read8 and iomux_write8 functions can't be easily moved to the gpio_banks block, since it's also used in the pre-SOC AMD chipsets that use the ACPIMMIO access functions directly. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia0d6dea72c6bebbbe6ce545bedfc74f91e0042c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
2021-09-08soc/amd/common/block/gpio_banks: factor out get_gpio_muxFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I7d7a8c5a7188fd558a577352f8b246e61f3edd63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08soc/amd/common/block/i2c: move raw GPIO access functions to gpio_banksFelix Held
The I2C code should use some GPIO API to access the GPIO registers instead of accessing the GPIO MMIO regions itself. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I84dff381ad86e0c7f879f0f079186aec9cafc604 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56779 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-09-08soc/amd/common/block/i2c: use common GPIO API in drive_sclFelix Held
No need to do raw GPIO MMIO accesses when basically the same functionality can be achieved by using existing APIs. Using the existing GPIO API instead of raw GPIO MMIO register accesses allows containing all direct GPIO MMIO accesses inside the common AMD GPIO code which will be done in subsequent patches. Since the value parameter of gpio_set is int, change the type of the val parameter of drive_scl to int as well even though I'm not sure why a signed integer was used for this in the common GPIO API. Since program_gpios already configures the SCL GPIOs as outputs, gpio_set can be used in drive_scl which only sets the output value, but doesn't configure the direction. TEST=The waveform on the SCL pin of I2C3 on a barla/careena Chromebook looks similar to the same as before during the reset_i2c_peripherals call, but due to the additional overhead of the read-modify-write to the GPIO register instead of just a write, the pulse width gets about 50% longer. Since the udelay call in drive_scl still has an open TODO to make this configurable and the pulses being longer is in the safe side, this side-effect can be addressed in a follow-up patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ic323cebc1c83ecd6f0e1fbab419c69489d77face Reviewed-on: https://review.coreboot.org/c/coreboot/+/56777 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-09-03soc/amd/common/block/gpio_banks/Kconfig: add option for non-soc/ chipsFelix Held
southbridge/amd/pi/hudson uses the common GPIO bank access code from soc/amd, but doesn't provide all functionality that would be needed to use the full functionality. Add a Kconfig option that switches off some functionality in the common SoC GPIO access code, so that more of the functionality proviced by the common SoC GPIO code can be used in the AMD binaryPI chipset and board code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib10d5d5580aab30a359aa001bb6fc7e9fdb8fc41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56783 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-09-01soc/amd/common: Change default spi speeds to 33MHzMartin Roth
In CB:56884 we discussed changing the default fast_read speed from 66MHz, which some platforms may not be capable of running, to 33MHz, which should be generally suitable for all platforms. This same change has been applied to the default for all SPI speeds. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibf926df6829ffdcbae947aaa245356f219615ce8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57148 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-30soc/amd/common: Show current SPI speeds and modesMartin Roth
This patch adds code to print the current SPI speeds for each of the 4 different speeds, Normal, Fast-read, Alt-mode, & TPM. It also displays the SPI mode and whether or not SPI100 mode is enabled. BUG=b:194919326 TEST: Display the speed, change speeds, show that new speeds are the expected values. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7825a9337474c147b803c85c9af7f9dc24670459 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-08-30soc/amd/common: Update SPI based on Kconfig & EFS instead of devtreeMartin Roth
Get the settings for fast-read and mode from EFS, and reprogram those. Program Normal reads, Alt-mode, and TPM speeds from Kconfig settings. BUG=b:195943311 TEST=Boot and see that SPI was set to the correct speed & mode Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b Reviewed-on: https://review.coreboot.org/c/coreboot/+/56959 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-08-30soc/amd/common: move GPIO register state save struct to gpio_banks.hFelix Held
The common_i2c_save struct isn't specific to the I2C code and since it contains the state of the GPIO control & status register and the state of the GPIO MUX register, move it to include/amdblocks/gpio_banks.h and rename it to soc_amd_gpio_register_save. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If7cd47e5a32427d856948e319de8dfad8c928e96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56778 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-30soc/amd/common/fsp/Makefile: drop strip_quotes call in FSP-M size checkFelix Held
No need to strip the quotes of the FSP-M file path in the size check and it's always a good idea to not remove the quotes around file paths that will get passed as parameters to shell programs so that spaces in the path can't cause malfunction. TEST=All cases still behave as expected for Mandolin. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Nico Huber <nico.h@gmx.de> Change-Id: Ieeea84b5861f9d15b2472208432169dc8e3f0049 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-08-28soc/amd/common/fsp/Makefile: check if CONFIG_FSP_M_FILE is definedFelix Held
When CONFIG_FSP_M_FILE isn't defined, the parameter of the file-size call evaluates to an empty string, so the file-size call will run "cat | wc -c" which will cause make to get stuck in there. Also print a message when no FSP-M file is specified that the resulting image won't boot successfully. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6b02774e2c79d12554fd076aa01bbe972176f372 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-08-27soc/amd/common/block/spi: Add SPI config to KconfigMartin Roth
Currently, The SPI speed/mode configuration is split between Kconfig and devicetree. We'd like to have everything in one place. Since we need the fast-read speed and the mode available in the Makefile to build the AMD EFS table, we currently need it in Kconfig. Move all of the settings to Kconfig and remove them from Devicetree in a later commit. BUG=b:195943311 TEST=boot majolica & guybrush, verify spi settings Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56884 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-27soc/amd/common/fsp/fsp_validate: add runtime check for FSP-M binary sizeFelix Held
When modules are added to the FSP and they won't fit into the FSP binary any more, the size can be increased in the FSP build. Especially in the case of debug builds the increased size might not fit into the memory region it gets decompressed into which starts at FSP_M_ADDR and has a size of FSP_M_SIZE. SoCs can implement the soc_validate_fspm_header function that ends up being called by the FSP driver in romstage to do some additional checks on the FSP binary's header that includes the version number and the image size. We can use the image size field to check if it fits into the reserved region. Since the FSP-M memory region is located after romstage loading it won't clobber the romstage code where we do the check. This runtime check is added in addition to the build-time check to also cover the case when the FSP binaries in CBFS get replaced with ones that don't fit into the reserved memory region after the coreboot build. BUG=b:186149011 TEST=Mandolin still boots fine with the patch applied. When as a test the FSP_M_SIZE Kconfig option in soc/amd/picasso is decreased to 0x10000 which is by far not enough for the decompressed FSP-M binary to fit into it prints the newly added error message on the console and then stops. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57068 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-26soc/amd/common/fsp/Makefile: check if FSP-M is larger than FSP_M_SIZEFelix Held
The FSP-M binary needs to fit into the memory region that starts at FSP_M_ADDR and is FSP_M_SIZE bytes large, so error out during build time if the uncompressed FSP-M file is larger than the size of the region it will be copied into. BUG=b:186149011 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Suggested-by: Furquan Shaikh <furquan@google.com> Change-Id: Ice4a59e5a723c3c0a40b1f3f3227aee6b9dcb39a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-08-20soc/amd/common: Skip psp_verstage on S0i3 resumeMartin Roth
PSP_Verstage will take almost the entire time to run that is allotted to S0i3 resume. Since coreboot isn't running, the PSP needs to handle any security requirements. The long- term plan is that the PSP won't even load psp_verstage on S0i3 resume, but when it is loaded, this makes sure we exit immediately BUG=b:177064859 TEST=Verify that PSP_verstage doesn't run on S0i3 resume Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f Reviewed-on: https://review.coreboot.org/c/coreboot/+/56919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-08-18soc/amd/common/upep.asl: Correct device list formatPratik Vishwakarma
Use correct format for constraint list as expected by kernel driver. With this change, kernel is able to correctly list dummy device in constraint list. BUG=b:194687976 TEST=Build and boot to OS in Guybrush. Change-Id: I7af1941ffd21cd5864c7285f44cb2d063d2f225f Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57012 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-08-05soc/amd/common/block/spi: Enable host burst to 4 DWORD when using DMAKarthikeyan Ramasubramanian
Disabling the 4 DWORD bursts causes SPI DMA operations to stall, so leave it enabled when SPI DMA is used. BUG=b:194919326 TEST=Build and boot to OS in Guybrush. Change-Id: I363acdcdb4178a10e4f7eb2bbcbd6d0ca7924f2d Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-08-05soc/amd/common/block/spi: introduce SOC_AMD_COMMON_BLOCK_SPI_4DW_BURSTFelix Held
Add a new Kconfig option to enable or disable the 4 DWORD burst support of the SPI controller and use this setting to determine if the corresponding feature bit in SPI100_HOST_PREF_CONFIG will be set or cleared. Since fch_spi_disable_4dw_burst can now enable or disable the feature, rename it to fch_spi_configure_4dw_burst. On Stoneyridge the SPI_RD4DW_EN_HOST bit needs to be cleared (see the Rd4dw_en_host bit definition in the SPIx2C SPI100 Host Prefetch Config register in the public BKDG #55072 Rev 3.09), so add a SoC dependency to the Kconfig option. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id754fa8d5f9554ed25cf9f3341bfdd1968693788 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-08-05soc/amd/picasso: Move IVRS generation code to commonJason Glenesk
Move IVRS acpi table generation code to common, so that it can be shared by other programs. BUG=b:190515051 TEST=Build picasso coreboot image. Compare IVRS tables before/after change. Change-Id: Icd5fec3a9d66e8301e267312020e726d9bc1aa70 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-31soc/amd/common/block/acpi: Add IVRS kconfigJason Glenesk
Add new IVRS kconfig option to control IVRS generation. BUG=b:190515051 Change-Id: Iad0c6401dbccd2f3f75464a69e4c27f64d3507a5 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-31soc/amd/common/block/gpio_banks: use unsigned int for gevent parameterFelix Held
A valid GEVENT number is never negative. The local variable in set_single_gpio still needs to be a signed integer, since the return value of get_gpio_gevent being -1 indicates that the GPIO can't generate a GEVENT. The check for that makes the function return before calling program_smi of program_sci, so the parameter of those functions can be changed to unsigned. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6ce23ceed1585589932824b8cab2a138328672a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56705 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: add missing newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I87595aea45bb3852a70c7322eae5a94abecb76a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56704 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: add comment in check_gpiosFelix Held
Each bit in the GPIO wake status index registers is set to 1 when at least one of 4 corresponding GPIO pins has its wake status register set. Added the comment since the gpio_base + i * 4 in the next line looked as if it calculates some absolute register value which is not what the code does or should be doing. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2fc8e9c5bd7c1b011f364b05d0cfdeb0df88ada6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56703 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-31soc/amd/common/block/gpio_banks/gpio: use size_t where neededFelix Held
Since the parameter the variable gets compared with is size_t type, use size_t as type for that variable too. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If82a948bf71079d456616f4438f4b754e0d7262d Reviewed-on: https://review.coreboot.org/c/coreboot/+/56702 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/gpio_banks: use gpio_t for gpio numbersFelix Held
With the addition of the remote GPIO support, the GPIO number won't fit into 8 bit any more, so use the gpio_t type instead which is an uint32_t typedef. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3de93fd3a2f2af3c1e3b335fef84019c56482051 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56693 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/gpio_banks/gpio: factor out set_gpio_muxFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I75f1e45ead4a5f04cba1eecb220ef027a8bfd09e Reviewed-on: https://review.coreboot.org/c/coreboot/+/56678 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/acpimmio_map: drop unused GPIO bank definesFelix Held
The offsets of all GPIOs in the up to four regular banks are all calculated relatively to ACPIMMIO_GPIO0_BANK, so we can just drop the unused defines for ACPIMMIO_GPIO1_BANK and ACPIMMIO_GPIO2_BANK. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I832ffdca479c1f07219a23b4a7f9be69322dfe03 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56675 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-30soc/amd/common/block/include/acpimmio_map: add GPIO bank 3 to tableFelix Held
GPIO bank 3 isn't used in coreboot, but the existence is documented in both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and for those two SoCs all 4 banks are covered by the corresponding Memory32Fixed region in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-26soc/amd/common/block/acpimmio: add Kconfig option for biosram accessorsFelix Held
The biosram accessor support in soc/amd/common/block/acpimmio/biosram.c is only used on Stoneyridge and the old amd/southbridge code and not on Picasso or Cezanne. It also only builds as a 32 bit binary and breaks when trying to build as a 64 bit binary, since the size of an uintptr_t is different on those two. There is no support for using the 32 bit binaryPI with a 64 bit coreboot while there is code to use a 32 bit FSP with 64 bit coreboot, so not building this for FSP-based SoC support moves us one step closer to be able to build coreboot as 64 bit binary for Picasso and Cezanne. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I2d87ec2fa1b217eaf55d865e4390308812502e56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-26soc/amd/common/block/pm: Add support for Modern Standby event loggingKarthikeyan Ramasubramanian
Log the GPE and PM1 wake events into the event log using the SMI handler platform callback. BUG=b:186792595, b:186800045 TEST=Build and boot to OS in Guybrush. Ensure that the wake sources are logged into the event logs. 5 | 2021-07-15 16:26:43 | S0ix Enter 6 | 2021-07-15 16:26:49 | S0ix Exit 7 | 2021-07-15 16:26:49 | Wake Source | GPE # | 22 <- Trackpad 8 | 2021-07-15 16:27:07 | S0ix Enter 9 | 2021-07-15 16:27:13 | S0ix Exit 10 | 2021-07-15 16:27:13 | Wake Source | RTC Alarm | 0 25 | 2021-07-15 16:38:13 | S0ix Enter 26 | 2021-07-15 16:38:17 | S0ix Exit 27 | 2021-07-15 16:38:17 | Wake Source | GPE # | 5 <- Fingerprint Change-Id: Icec6fc03f4871cc46b32886575a7054bc289f4bf Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-07-26soc/amd/common/block/acpi: Extract event logging helpersKarthikeyan Ramasubramanian
Move the event logging helpers defined in acpi into a separate library. This will allow logging power management and GPE events for both S3 and Modern Standby. Introduce a single helper acpi_log_events function to log both PM and GPE events. BUG=None TEST=Build and boot to OS in Guybrush. Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-25soc/amd/common/block/cpu/mca/mcax: add comment about McaXEnable bitFelix Held
TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN APU that the McaXEnable bit is set in the CONFIG registers of all used MCAX banks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-24soc/amd/common/block/cpu/mca/mca_common: remove additional newlineFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49a27eb084b59db455153dd662d564a95940a0ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/56534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-07-21soc/amd/cezanne: enable crypto in psp_verstageKangheui Won
Enable RSA and SHA for cezanne since support has been added to the PSP. Also picasso and cezanne have different enums definitions for hash algorithm, so split that out into chipset.c. BUG=b:187906425 TEST=boot guybrush, check cbmem -t and the logs Signed-off-by: Kangheui Won <khwon@chromium.org> Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550 Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-07-21commonlib/timestamp,amd/common/block/cpu: Add uCode timestampsRaul E Rangel
This allows keeping track of how long it takes to load the microcode. BUG=b:179699789 TEST=Boot guybrush 112:started reading uCode 990,448 (10,615) 113:finished reading uCode 991,722 (1,274) Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I86b67cf9d17786a380e90130a8fe424734e64657 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-07-19soc/amd/{common,cezanne}: Implement HAVE_PAYLOAD_PRELOAD_CACHERaul E Rangel
This change allows preloading the payload. BUG=b:179699789 TEST=Boot guybrush and see payload read/decompress drop by 20 ms. We now spend 7ms decompression from RAM. By switching to LZ4 we drop that to 500us. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-18soc/amd/common/apob: Add support for asynchronously reading APOB_NVRaul E Rangel
This CL adds a method that can start the processes of reading the APOB from SPI. It does require more RAM in ramstage since we no longer mmap the buffer in the happy path. This will allow us to reduce our boot time by ~10ms. The SoC code will need to be updated to call start_apob_cache_read at a point where it makes sense. BUG=b:179699789 TEST=With this and the patches above I can see a 10 ms reduction in boot time on guybrush. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56232 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18soc/amd/common/apob: Switch to using fmap_locate_area_as_rdevRaul E Rangel
Using fmap_locate_area is discouraged. BUG=b:179699789 TEST=Boot guybrush and verify APOB got updated, then reboot and verify APOB was valid. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7f58eace8adb4b7ddaf9047d9b8153405d3941a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56390 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18soc/amd/common/block/lpc/spi_dma: Yield after completing transactionRaul E Rangel
There is no telling when the next udelay will be, so explicitly call `thread_yield()` after completing a transaction. This will allow any pending transactions to immediately start. BUG=b:179699789 TEST=Verify new transaction is enqueued right after another. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9c1272bde46c3e0c15305b76c2ea7a6dde5ed0b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56321 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18soc/amd/common/block/lpc/spi_dma: Use mutex to protect DMA registersRaul E Rangel
Once we enable COOP_MULTITASKING, we need to guarantee that we don't have multiple threads trying to access the DMA hardware. BUG=b:179699789 TEST=Boot guybrush with APOB patches. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56231 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-18soc/amd/common/block/lpc/spi_dma: Implement SPI DMA functionalityRaul E Rangel
This change will make it so the standard rdev readat call will use the SPI DMA controller if the alignment is correct, and the transfer size is larger than 64 bytes. There is a magic bit that needs to be set for the SPI DMA controller to function correctly. This is only available in RN/CZN+. BUG=b:179699789 TEST=Boot guybrush to OS. This reduces loading verstage by 40ms, verifying RW by 500us and loading romstage by 500 us. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-07-17soc/amd/common/block/graphics: add GPU PCI ID for BarceloFelix Held
Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify that that is the one for Cezanne. BUG=b:193888172 Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-16include/cpu/amd/msr: don't redefine the IA32_BIOS_SIGN_ID MSRFelix Held
Change-Id: Iff19ae495fb9c0795dae4b2844dc8e0220a57b2c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56310 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-07-15soc/amd/common/block/cpu/mca/mcax: print all MCAX registersFelix Held
Also move the registers in the order they are in the hardware. Change-Id: If018e746e58c14475caeda76feb8b5281d7732f1 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56315 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/amd/common/block/cpu/mca: make building the BERT support conditionalFelix Held
Only when ACPI_BERT is selected the BERT functionality needs to be included in the build. Change-Id: I8a21562f4535fb0ea3c53f2ea8df50f66cc6a64c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56314 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-07-15soc/amd/common/block/cpu/mca: commonize mca_check_all_banksFelix Held
Since we don't need to skip the MCA check on cold boot on MCAX capable systems, add a mca_skip_check implementation that always returns false. Change-Id: Id8fc4b6f02b6c02b03172fe11f0451a9893e514d Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15soc/amd/common/block/cpu/mca/mca: factor out mca_skip_checkFelix Held
This will allow moving mca_check_all_banks to mca_common.c. Change-Id: I58e100c1447907bab984a2fdff6c6e0181910c23 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56312 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2021-07-15soc/amd/stoneyridge/mca: implement and use mca_has_expected_bank_countFelix Held
This aligns the mca_check_all_banks implementation in the common mca.c with the one in the common mcax.c file. Do the MCA bank count check before the !is_warm_reset() check, so that a mismatch also gets printed on the cold boot path. Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-21 12:30:35 +0000