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authorZheng Bao <fishbaozi@gmail.com>2021-10-30 21:30:34 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-11-01 15:55:56 +0000
commit19b3102910f813e71efaa61c86e683afd48899a1 (patch)
tree7f682cfdc7aed4fad090eb1662b31118fe8b8210 /src/soc/amd/common
parent72e76676fca192401b603276f99df46e63a45b9f (diff)
amd/lpc: Remove the weak function
BUG=b:140165023 Change-Id: Idb4613dc08c8dee6c92b4dabb39c2f5c189471aa Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/amd/common')
-rw-r--r--src/soc/amd/common/block/include/amdblocks/lpc.h2
-rw-r--r--src/soc/amd/common/block/lpc/lpc.c5
2 files changed, 0 insertions, 7 deletions
diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h
index daa51f1145..09eafb8b07 100644
--- a/src/soc/amd/common/block/include/amdblocks/lpc.h
+++ b/src/soc/amd/common/block/include/amdblocks/lpc.h
@@ -141,8 +141,6 @@
/* Clear all decoding to the LPC bus and erase any range registers associated
* with the enable bits. */
void lpc_disable_decodes(void);
-/* LPC is typically enabled very early, but this function is last opportunity */
-void soc_late_lpc_bridge_enable(void);
void lpc_enable_port80(void);
void lpc_enable_pci_port80(void);
void lpc_enable_decode(uint32_t decodes);
diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c
index 365c14dbf3..496816b0f3 100644
--- a/src/soc/amd/common/block/lpc/lpc.c
+++ b/src/soc/amd/common/block/lpc/lpc.c
@@ -20,9 +20,6 @@
#include <soc/lpc.h>
#include <soc/southbridge.h>
-/* Most systems should have already enabled the bridge */
-void __weak soc_late_lpc_bridge_enable(void) { }
-
static void setup_serirq(void)
{
u8 byte;
@@ -41,8 +38,6 @@ static void lpc_init(struct device *dev)
{
u8 byte;
- soc_late_lpc_bridge_enable();
-
/* Initialize isa dma */
isa_dma_init();