summaryrefslogtreecommitdiff
path: root/src/northbridge/intel
AgeCommit message (Expand)Author
2018-08-04x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
2018-08-04nehalem/raminit: remove read_mchbar functionsFelix Held
2018-08-04nehalem/raminit: clean up code and remove write_mchbar functionsFelix Held
2018-08-04northbridge/nehalem: add MCHBAR8/16 AND_OR macrosFelix Held
2018-08-04nehalem/raminit: clean up code and use MCHBAR macrosFelix Held
2018-08-04nehalem/raminit: remove REAL define and most dead codeFelix Held
2018-08-03sandybridge/raminit_mrc: remove reference to report_platform_info()Matt DeVillier
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining placesFelix Held
2018-08-01sandybridge/raminit_common: use macro for execute command queue registerFelix Held
2018-08-01sandybridge/raminit_common: use FOR_ALL_CHANNELS macroFelix Held
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
2018-08-01northbridge/sandybridge: add MCHBAR32 AND/OR/AND_OR access macrosFelix Held
2018-08-01nb/intel/gm45: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-08-01nb/intel/pineview: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-08-01nb/intel/x4x: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-08-01nb/intel/sandybridge: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-07-30x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
2018-07-30nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans
2018-07-30northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held
2018-07-30northbridge/nehalem: add MCHBAR AND/OR/AND_OR macrosFelix Held
2018-07-30northbridge/nehalem: clean up header fileFelix Held
2018-07-29sandybridge/raminit_common: use MCHBAR32 macro everywhereFelix Held
2018-07-29sandybridge/raminit: use MCHBAR32 macro everywhereFelix Held
2018-07-29sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macrosFelix Held
2018-07-29nb/intel/sandybridge: Bump MRC_CACHE_VERSIONPatrick Rudolph
2018-07-28nb/intel/sandybridge/report_platform: Move remaining code to sb folderPatrick Rudolph
2018-07-28nb/intel/sandybridge: Move CPU report to cpu folderPatrick Rudolph
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
2018-07-26nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus widthPatrick Rudolph
2018-07-26nb/intel/sandybridge/raminit: Fix PDWN_mode on desktopsPatrick Rudolph
2018-07-26nb/intel/nehalem: Remove the C native graphic initArthur Heymans
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
2018-07-25nb/intel/sandybridge/raminit: Fix non ASCII charPatrick Rudolph
2018-07-25nb/intel/sandybridge/raminit: Set REFIx9 according to specPatrick Rudolph
2018-07-12nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMsElyes HAOUAS
2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
2018-07-02src/nb: Fix non-local header treated as localElyes HAOUAS
2018-06-30arch/x86/acpi: Add DMAR RMRR helper functionsMatt DeVillier
2018-06-29sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans
2018-06-29sb/intel/i82801ix: Use the common ACPI pirq generatorArthur Heymans
2018-06-23nb/intel/i945: Remove dead codeElyes HAOUAS
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
2018-06-20nb/intel/e7505: Leave ROM as un-cacheable in postcarKyösti Mälkki
2018-06-17nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki
2018-06-17nb/intel/i440bx: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
2018-06-17cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki
2018-06-17nb/intel/nehalem: Fix DEVEN definesPatrick Rudolph
2018-06-17nb/intel/x4x: Issue a hard reset with empty MRC cache on warm resetArthur Heymans
2018-06-14cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans
2018-06-14nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xceElyes HAOUAS
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
2018-06-14nb/intel/x4x: Work around a quirkArthur Heymans
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
2018-06-07nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans
2018-06-07nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans
2018-06-07nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans
2018-06-06intel/e7505: Remove ROMCC workaroundKyösti Mälkki
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
2018-06-06arch/x86: Flag platforms without RELOCATABLE_RAMSTAGEKyösti Mälkki
2018-06-05cpu/intel/haswell: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05cpu/intel/model_2065x: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05cpu/intel/model_206ax: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05nb/intel/gm45: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05nb/intel/x4x: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05nb/intel/pineview: Switch to POSTCAR_STAGEArthur Heymans
2018-06-05nb/intel/i945: Switch to POSTCAR_STAGEArthur Heymans
2018-06-04security/tpm: Unify the coreboot TPM software stackPhilipp Deppenwiese
2018-06-04intel/i440bx: Drop tests for LATE_CBMEM_INITKyösti Mälkki
2018-06-04src: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
2018-06-04nb/intel: Use postcar_frame_add_romcache()Nico Huber
2018-06-04northbridge/intel: Remove unneeded includesElyes HAOUAS
2018-06-02intel/socket_mPGA604 intel/e7505: Switch to POSTCAR_STAGEKyösti Mälkki
2018-06-02intel/e7505: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
2018-06-02intel/e7505: Assume AGP slot disabledKyösti Mälkki
2018-06-02aopen/dxplplusu intel/e7505: Move to EARLY_CBMEM_INITKyösti Mälkki
2018-06-02intel/e7505: Fix domain resourcesKyösti Mälkki
2018-05-31{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriateNico Huber
2018-05-29src/northbridge: Add and update license headersMartin Roth
2018-05-24nb/intel/fsp_sandybridge: Fix lost const qualifier on 'device_t'Elyes HAOUAS
2018-05-24nb/intel/x4x: Adapt post JEDEC for DDR3Arthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 enhanced mode and power settingsArthur Heymans
2018-05-24nb/intel/x4x/raminit: Add DDR3 specific dra/drb settingsArthur Heymans
2018-05-24nb/intel/x4x: Implement write levelingArthur Heymans
2018-05-24nb/intel/x4x: Add DDR3 JEDEC initArthur Heymans
2018-05-24nb/intel/sandybridge: Get rid of device_tElyes HAOUAS
2018-05-21nb/intel/nehalem: Fix smashed stack in romstageMatthias Gazzari
2018-05-18nb/common/intel: Remove the mrc cache codeArthur Heymans
2018-05-18nb/intel/nehalem: Use the common mrc cache driverArthur Heymans
2018-05-18nb/intel/e7505: Get rid of device_tElyes HAOUAS
2018-05-18nb/intel/haswell: Get rid of device_tElyes HAOUAS
2018-05-17nb/intel/nehalem: Add ACPI pathPatrick Rudolph
2018-05-14nb/intel/fsp_sandybridge: Get rid of device_tElyes HAOUAS
2018-05-14nb/intel/i945/raminit.c: Remove not necessary braces {}Elyes HAOUAS
2018-05-14nb/intel/x4x/raminit: DDR3 specific ODTArthur Heymans
2018-05-14nb/intel/x4x: Add DDR3 rcompArthur Heymans
2018-05-14nb/intel/x4x/raminit: Support programming initials DD3 DLL settingArthur Heymans
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-18 05:53:35 +0000