diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-12-25 20:17:41 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-24 13:04:17 +0000 |
| commit | b4a78045d572d621ec54bd7c061c4b995a1515a7 (patch) | |
| tree | 44d0661b07c20b85995dd7cd8a237f149c3af61f /src/northbridge/intel | |
| parent | b5170c3e92b3f0cbce292f3414375b1326f4dd12 (diff) | |
nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings
When programming the final dram attribute and dram boundary settings,
on DDR3 dram one also needs to enable ZQCAL in the CxREFRCTRL (DRAM
Refresh Control) register as documented in "Intel ® 4 Series Chipset
Family" documentation.
Change-Id: I11a79f6800dbfe19c2bd33c0d6caca14b034e384
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel')
| -rw-r--r-- | src/northbridge/intel/x4x/raminit_ddr23.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 618e21215c..b072154bb9 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1616,6 +1616,14 @@ static void set_dradrb(struct sysinfo *s) MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | ((rankpop0 << 4) & 0xf0); MCHBAR8(0x662) = (MCHBAR8(0x662) & ~0xf0) | ((rankpop1 << 4) & 0xf0); + if (s->spd_type == DDR3) { + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + /* ZQCAL enable */ + MCHBAR32(0x269 + 0x400 * ch) = + MCHBAR32(0x269 + 0x400 * ch) | (1 << 26); + } + } + if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) MCHBAR8(0x260) = MCHBAR8(0x260) | 1; |