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path: root/src/northbridge/intel
AgeCommit message (Expand)Author
2018-11-05nb/intel/x4x/raminit: Add missing spaceJonathan Neuschäfer
2018-11-05nb/intel/i945: Remove irrelevant conditional statementElyes HAOUAS
2018-11-02nb/intel/haswell: Consolidate memory controller PCI driver structsTristan Corrick
2018-11-01nb/intel/haswell/gma: Support boards that have DDI E connectedTristan Corrick
2018-11-01sb/intel/lynxpoint: Automatically generate the ACPI PCI routing tableTristan Corrick
2018-11-01nb/intel/haswell: Add a PCI ID for a Mini-HD audio controllerTristan Corrick
2018-11-01nb/intel/haswell: Add a PCI ID for a desktop memory controllerTristan Corrick
2018-11-01src: Add missing include <stdint.h>Elyes HAOUAS
2018-10-24nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardwareArthur Heymans
2018-10-24nb/intel/*: Account for cbmem_top alignmentArthur Heymans
2018-10-24nb/intel/i945: Fix domain resourcesArthur Heymans
2018-10-23src: Remove unneeded whitespaceElyes HAOUAS
2018-10-22intel: Use CF9 reset (part 1)Patrick Rudolph
2018-10-19nb/intel/nehalem: Remove unneeded whitespaceElyes HAOUAS
2018-10-15nb/intel/x4x: Fix P45 CAPID max frequencyArthur Heymans
2018-10-15nb/intel/x4x: Program read training results to all ranksArthur Heymans
2018-10-11src: Move common IA-32 MSRs to <cpu/x86/msr.h>Elyes HAOUAS
2018-10-11src: Replace MSR addresses with macrosElyes HAOUAS
2018-10-08Move compiler.h to commonlibNico Huber
2018-10-08src: Use tabs for indentationElyes HAOUAS
2018-10-08nb/intel/{gm45,i945,pineview}: Use macro instead of GGC addressElyes HAOUAS
2018-09-28src/*: normalize Google copyright headersPatrick Georgi
2018-09-25northbridge: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS
2018-09-16nb/intel/x4x: Don't use cached settings if CPU FSB has been changedArthur Heymans
2018-09-14nb/intel/sandybridge: Don't add SMBIOS Table 17 entries on resumeNico Huber
2018-09-14complier.h: add __always_inline and use it in code baseAaron Durbin
2018-09-05nb/intel/x4x/gma.c: fix skipping of native graphics initStefan Tauner
2018-08-22nb/intel/*/gma.c: Skip NGI when VGA decode is not enabledArthur Heymans
2018-08-21nb/intel/sandybridge/raminit: Move fill_smbios17 to ddr3.cPatrick Rudolph
2018-08-21nb/intel/pineview: Use a common MMCONF_BASE_ADDRESSArthur Heymans
2018-08-21nb/intel/pineview: Use the correct address for the RCVEN strobeArthur Heymans
2018-08-21nb/intel/pineview: Use i2c block read to fetch SPDArthur Heymans
2018-08-20nb/intel/raminit: Remove unused headersPatrick Rudolph
2018-08-20nb/intel/sandybridge/raminit: Fix DIMM type mappingPatrick Rudolph
2018-08-20nb/intel/sandybridge: Fill in DIMM serial numberPatrick Rudolph
2018-08-17sandybridge/raminit_common.c: fix printram statementIru Cai
2018-08-17Fix PCI ACPI _OSC methodsMarc Jones
2018-08-13nb/intel/haswell: Always locate mrc.bin in the COREBOOT fmap regionArthur Heymans
2018-08-10src: Fix typoElyes HAOUAS
2018-08-09src/northbridge: Fix typoElyes HAOUAS
2018-08-04x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
2018-08-04nehalem/raminit: remove read_mchbar functionsFelix Held
2018-08-04nehalem/raminit: clean up code and remove write_mchbar functionsFelix Held
2018-08-04northbridge/nehalem: add MCHBAR8/16 AND_OR macrosFelix Held
2018-08-04nehalem/raminit: clean up code and use MCHBAR macrosFelix Held
2018-08-04nehalem/raminit: remove REAL define and most dead codeFelix Held
2018-08-03sandybridge/raminit_mrc: remove reference to report_platform_info()Matt DeVillier
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining placesFelix Held
2018-08-01sandybridge/raminit_common: use macro for execute command queue registerFelix Held
2018-08-01sandybridge/raminit_common: use FOR_ALL_CHANNELS macroFelix Held
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [2/2]Felix Held
2018-08-01sandybridge/raminit_common: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
2018-08-01northbridge/sandybridge: add MCHBAR32 AND/OR/AND_OR access macrosFelix Held
2018-08-01nb/intel/gm45: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-08-01nb/intel/pineview: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-08-01nb/intel/x4x: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-08-01nb/intel/sandybridge: Don't use PCI operations on the pci_domain deviceArthur Heymans
2018-07-30x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]Felix Held
2018-07-30nb/intel/gm45: Use common code for SMM in TSEGArthur Heymans
2018-07-30northbridge/x4x: add MCHBAR AND/OR/AND_OR access macrosFelix Held
2018-07-30northbridge/nehalem: add MCHBAR AND/OR/AND_OR macrosFelix Held
2018-07-30northbridge/nehalem: clean up header fileFelix Held
2018-07-29sandybridge/raminit_common: use MCHBAR32 macro everywhereFelix Held
2018-07-29sandybridge/raminit: use MCHBAR32 macro everywhereFelix Held
2018-07-29sandybridge: add brackets to MCHBAR/EPBAR/DMIBAR access macrosFelix Held
2018-07-29nb/intel/sandybridge: Bump MRC_CACHE_VERSIONPatrick Rudolph
2018-07-28nb/intel/sandybridge/report_platform: Move remaining code to sb folderPatrick Rudolph
2018-07-28nb/intel/sandybridge: Move CPU report to cpu folderPatrick Rudolph
2018-07-28intel/sandybridge: Don't hardcode platform typePatrick Rudolph
2018-07-26nb/intel/sandybridge/raminit: Fix SMBIOS 17 bus widthPatrick Rudolph
2018-07-26nb/intel/sandybridge/raminit: Fix PDWN_mode on desktopsPatrick Rudolph
2018-07-26nb/intel/nehalem: Remove the C native graphic initArthur Heymans
2018-07-25drivers/tpm: Add TPM ramstage driver for devices without vboot.Philipp Deppenwiese
2018-07-25nb/intel/sandybridge/raminit: Fix non ASCII charPatrick Rudolph
2018-07-25nb/intel/sandybridge/raminit: Set REFIx9 according to specPatrick Rudolph
2018-07-12nb/i945/raminit: Correct C0DRAMW & C1DRAMW for 4 DIMMsElyes HAOUAS
2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
2018-07-02src/nb: Fix non-local header treated as localElyes HAOUAS
2018-06-30arch/x86/acpi: Add DMAR RMRR helper functionsMatt DeVillier
2018-06-29sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans
2018-06-29sb/intel/i82801ix: Use the common ACPI pirq generatorArthur Heymans
2018-06-23nb/intel/i945: Remove dead codeElyes HAOUAS
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
2018-06-20nb/intel/e7505: Leave ROM as un-cacheable in postcarKyösti Mälkki
2018-06-17nb/intel/i440bx: Switch to POSTCAR_STAGEKyösti Mälkki
2018-06-17nb/intel/i440bx: Move to RELOCATABLE_RAMSTAGEKyösti Mälkki
2018-06-17cpu/intel/slot_1: Switch to different CAR setupKyösti Mälkki
2018-06-17nb/intel/nehalem: Fix DEVEN definesPatrick Rudolph
2018-06-17nb/intel/x4x: Issue a hard reset with empty MRC cache on warm resetArthur Heymans
2018-06-14cpu/intel/haswell: Use the common intel romstage_main functionArthur Heymans
2018-06-14nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xceElyes HAOUAS
2018-06-14nb/intel/x4x: Deprecate native graphic initArthur Heymans
2018-06-14nb/intel/x4x: Fix a few things in set_enhanced_modeArthur Heymans
2018-06-14nb/intel/x4x: Work around a quirkArthur Heymans
2018-06-14nb/intel/x4x: Add the option for stacked channel map settingsArthur Heymans
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
2018-06-08libgfxinit: Enable G45 support (for GM45/X4X)Nico Huber
2018-06-07nb/intel/pineview: Enable and allocate 8M for TSEGArthur Heymans
2018-06-07nb/intel/i945: Enable and allocate 8M for TSEGArthur Heymans
2018-06-07nb/intel/i945: Add a common function to compute TSEG sizeArthur Heymans
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