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This allows to set the preallocated memory for the IGD on x4x
using a cmos option.
If no cmos option is found a default value of 64M is used.
TESTED most options on ga-g41m-es2l with 2G dimm in one slot and 2x2G.
352M also works in contrast with gm45 where it is known to cause issues
with certain ram combinations.
Change-Id: I9051d080be82f6dfab37d353252e29b2ed1fca7f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15492
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The Intel documtentation, "Intel ® 4 Series Chipset Family"
mentions the possibility of 1, 4, 8 and 16M of preallocated
memory for the IGD, but does not document this.
This allows to set those undocumented values.
TESTED on ga-g41m-es2l with 2G dimm in one slot and 2x2G.
Change-Id: I92beb8d78907d4514a5aaf69248dd607dcf227c0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15491
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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These non-ascii & unprintable characters aren't needed.
Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/15977
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: I5aa27f06f82a8309afb6e06c9e462e5792aa9986
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/15940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and
developer mode check functions to vboot. Thus, get rid of the
BOOTMODE_STRAPS option which controlled these functions under src/lib.
BUG=chrome-os-partner:55639
Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/15868
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Now hardcode maximum memory frequency capability to 800MHz, as
all chipsets in x4x family support PC2-6400 according to the datasheet.
CAS latency detection also relies on this, and has been cleaned up.
Ram initialization does not work with FSB 1333MHz / DDR2 800MHz combination,
so disable this combination for now, and reduce to 667MHz instead.
Still don't know why this is the case, but FSB1333/667 works.
These changes should now allow existing configurations to continue working,
while providing support for previously unworking configurations, due to
previous buggy CAS latency detection code.
TESTED: on GA-G41M-ES2L
CPU: E5200 @ 2.50GHz (FSB 800MHz)
2x 1GB 667MHz hynix worked @ 667
1x 2GB 800Mhz ARAM worked @ 800
1x 1GB 667Mhz StarRam worked @ 667
2x 2GB 800Mhz (generic) worked @ 800
Change-Id: I1ddd7827ee6fe3d4162ba0546f738a8f9decdf93
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15818
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Match the definition and use of these variable with haswell, such that
DCACHE_RAM_MRC_VAR_SIZE is not included in DCACHE_RAM_SIZE.
Change-Id: I5af20f63cd0cb631d39f7c7fe0e2a99ebd3ce986
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15761
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix and use the failsafe CAS detection logic rather than
recalulating the values from raw SPDs.
Tested on GA-G41M-ES2L with 2x2GB DDR2-800 DIMMs
(which worked before and still work)
Change-Id: I6af0f1705d099f7bcbff8c9baa94a68dae689e01
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15726
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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If S3 support was implemented for this platform later on, use
romstage handoff structure instead.
Change-Id: I03c1e07a7fcc17c27203d0c4e32e3958f2ba5273
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15716
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
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If S3 support was implemented for this platform later on, use
romstage handoff structure instead.
Change-Id: Ib0cf3ad41753baee26354c5ed19294048e7fb533
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15715
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
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Change-Id: I7c3973ff325f11a86728e8660c70839776981aa5
Reported-by: GCC 6.1.0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Previously, any 800MHz DIMMs were being slowed to 667MHz
for no reason other than there was a bug in the maximum
frequency detection code for the MCH.
Change-Id: Id6c6c88c4a40631f6caf52f536a939a43cb3faf1
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15257
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Reading cpuid leaf 0 is incorrect for testing cpu family.
Use leaf 1 instead. See Intel SDM 2a Table 3-17.
Change-Id: Ib2c95cdd1fb93db06a08ecd7266f6b88700caf83
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/15346
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: I6f0cdc80870fddeaada3191e493bd85fdefee07f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15245
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Broken with commit:
5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS
Available sandybridge/systemagent-r6.bin has MMCONF hard-coded
at some places and samsung/lumpy fails at boot here:
CBFS: Locating 'mrc.bin'
CBFS: Found @ offset 9fec0 size 2fc94
System Agent: Starting up...
System Agent: Initializing
These are the last lines as captured over USB debug.
Change-Id: I441847f0e71a5e1be9c8ef6a04a81eb7bdd8a6d9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15328
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Without RELOCATABLE_RAMSTAGE have WB cache large enough
to cover the greatest ramstage needs, as there is no benefit
of trying to accurately match the actual need. Choose
this to be bottom 16MiB.
With RELOCATABLE_RAMSTAGE write-back cache of low ram is
only useful for bottom 1MiB of RAM as a small part of this gets used
during SMP initialisation before proper MTRR setup.
Change-Id: Icd5f8461f81ed0e671130f1142641a48d1304f30
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Ib3250677ee926deaa957c83aca7479eb0159358c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15231
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of programming unsupported CAS use the highest supported
value. Start at DDR3 maximum of CAS 18T.
Increase error message verbosity level.
Useful for overclocking.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
Allows to run a DDR3-1600 DIMM at 933Mhz.
Change-Id: I2e8aadd541f06fa032ad7095c9a2d5e3bb7613f3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15217
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Calculate the value from current DDR frequency.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
Change-Id: I57ffbfeb291fc2fede278d18527993e7432e9bd8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15184
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
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Simplify calculation of value.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
Change-Id: I3ecd12c431b46a8d2218f33d7eb3e10de3bcd61d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15181
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Set max_mem_clock_mhz in devicetree to 933Mhz.
Allows to run the memory at up to DDR3-1866.
The same frequency was allowed within the first vendor bios,
but Lenovo than decided to limit it to DDR3-1333.
Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16).
The RAM is now running at DDR3-1600 instead of DDR3-1333.
This gives about 4% performance increase in glmark2 using the
Intel GPU.
Change-Id: If15be497402d84a2778f0434b6381a64eda832d6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15158
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I3c517fc55dd333b1a457324f1d69aeb6f70acec2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15197
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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This is more of ACPI S3 resume and x86 definition than CBMEM.
Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15190
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.
Tested on Sandybridge Lenovo T520.
Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove code duplication and use the common function
store_current_mrc_cache instead.
No functionality is changed.
Tested on Sandybridge Lenovo T520.
Change-Id: I4aa5463f1b1d5e1afbe44b4bfc659524d86204db
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15074
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Previously, 0x0 was the value being used for an unpopulated dimm
on spd[62], however some DDR2 dimms have 0x0 as a valid value.
Now use 0xff which is an unused value even on DDR2/DDR3.
Change-Id: I55a91a6c3fe3733a7bb2abc45ca352c955c07c99
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/15058
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Setting the size of the preallocated memory for the igd is done
using a cmos parameter, gfx_uma_size. This was limited to a subset of
all available sizes, that were already implemented elsewhere
in the northbridge code.
What this does is change the cmos parameter to 4 bits instead
of 3 bits to accomodate all vram sizes.
It also adds a sane default of 32mb that already was in place.
The northbridge code that reads this cmos parameter is
also changed for this new cmos settings.
352M is disabled since it causes issues on systems with 4GB or more ram.
TEST: Build, flash target. Clear cmos by corrupting
the checksum (nvramtool -c something).
Set a desired value in gfx_uma_size using nvramtool.
"dmesg | grep stolen" to see what is actually allocated.
Change-Id: Ia6479d03f1abe6d0c94bd7264365505e8f8eaeec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14900
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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The values were obtained from vendor bios at runtime.
I am not 100% sure of the sequence required to initiate them,
but guessed from the gm45 code. There may be some status bytes
needed to be polled during the sequence that is missing,
but as I don't have bios writer's datasheet it's very hard
for me to know.
Change-Id: Idd205e0bab5f75e01c6e3a5dc320c08639f52db8
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/14925
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Items under DEVICE_SPECIFIC_OPTIONS got selected without
the driver being selected.
Change-Id: I1797fa6175620a9291873559a6308eaea85a090e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14823
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Mask out the bit that doesn't fit in 32bits, so gcc 6.1 is happy
Change-Id: I13e2b41742206b8d86b90314b80cc324c00ae637
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14639
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Tested-by: build bot (Jenkins)
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The PLL will never lock if the requested frequency is already set.
As the fallback may request the same frequency again exit early
to prevent a hang.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
Change-Id: I625b2956346d8c50cca84def6190c076bf99dbec
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14174
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Add the following fallbacks:
* Try decreasing clock frequency.
In case of DDR1600 the next possible value of DDR1333 is being used.
* Try decreasing clock frequency.
In case of DDR1333 the next possible value of DDR1066 is being used.
* Disable failing channel.
The system may be able to boot with a single channel enabled.
The fallbacks are untested.
Change-Id: I3be7034ad25312b3ebf47a54f335a3893f8d7cc1
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14173
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The LVDS port is configured to accept data from pipe A, but the panel
fitter and VGA were attached to pipe B.
Changes to VGACNTRL:
- select pipe A instead of pipe B.
- disable VGA centering to fix jitter.
TEST=Build and run on Thinkpad X200 in both text and framebuffer modes.
Change-Id: I2356f264580d8b021952c217de3477291d866f98
Signed-off-by: Nick High <nhigh@openmailbox.org>
Reviewed-on: https://review.coreboot.org/14524
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
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Fix regression introduced by:
Ib48fe8380446846df17d37b22968f7d4fd6b9b13
Don't run channel_test on S3 resume as it overrides memory
that might be in use.
Fixes MCE events reported by the GNU/Linux kernel that
low memory has been modified.
Reset on failed s3 resume.
Change-Id: Ibadea286619c7906225f86a93aaa0b4caf26cabe
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14439
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Always use MRC cache if possible.
Added a CRC16 array to make sure the DIMMs haven't been replaced.
In case one of the CRC's doesn't match, start normal RAM training.
Use new fallback in case of broken mrc cache.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
Test result:
The system boots a lot faster using the MRC cache.
On swapping DIMMs the CRC16 doesn't match and normal ram training
is started.
Change-Id: Ib48fe8380446846df17d37b22968f7d4fd6b9b13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14172
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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In error case die in top level function.
No functionality is changed.
Change-Id: Ie15b01184d40bdbce20d49dcab2f9fb607068c7a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14171
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Return errors to top level ram init function.
Required by the folowing series to implement a fallback.
No functionality is changed.
On error case the system still halts in every test.
Change-Id: I6278c4a1d7b4a96be8988a60671fc3d72cd6cb3d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14170
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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In order to add a fallback mechanism, move the ram training code
into a new function. This function will be called multiple times
and must return error or success to the calling function.
Change-Id: I5ee1b3a528290d8252d236b9152b81291736958a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14169
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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It's required to store the dimm_info in ramctr_timing as only ramctr_timing
is written to mrc cache.
Allows to fill SMBIOS type 17 if mrc cache is used.
Change-Id: I7634b05069df307d471938d9854997a018de81b3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/14168
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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The Intel i3100 northbridge code is the only user of
cache_ramstage(). Therefore, place it next to the sole
consumer.
Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14097
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i3100 boards in the chipset.
Change-Id: Ia66a0561c75777a9e98bb87117859808a2ff3732
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13786
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i810 boards in the chipset.
Change-Id: Ifda7dcfdf37b6affce838ee96ca6382b2d4be8c3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13784
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i830 boards in the chipset.
Change-Id: I0a63ddd3c5e43ea65f776385f54eceb6569751ac
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13783
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The sourcecode is 99% the same. Only two lines differ, but not
in functionality.
Also rename mrccache.c -> mrc_cache.c
Tested-on: boot + suspend/resume on x220
Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14007
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The mrc_cache definition and the struct mrc_container are the same
over all intel platforms.
Change-Id: I128a4b5693d27ead709325c597ffe68a0cc78bab
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/13998
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I2738da99e4651598faeaa228fba447d0872e9ded
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/13999
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Commit 71512b2c (northbridge/i945/gma: fix build error with native graphics init)
unintentionally changed the code to ignore the NVRAM setting
`tft_brightness`. Revert that hunk to restore the original behavior.
Change-Id: Iffdfc5272732bad3476f35ddac1f5a7564270531
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14002
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i440BX boards in the chipset.
Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13781
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This is a step towards isolating the timer drivers.
Change-Id: I4c9349054be0cf520cd4407be9fb393b664223a4
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13922
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Sandy and Ivy Bridge processors use the same socket, and a mainboard
with the socket can support both types of CPUs. However, they use
different native graphics init code for LVDS and cause a crash if
running the wrong code.
This change detects the CPU type and then selects the right code to
run. It will add some more code in ramstage. It also merges the
{SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS.
Tested on a Lenovo T520 with i7-2630qm and i7-3720qm
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91
Reviewed-on: https://review.coreboot.org/12087
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
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Fill minimal info required for SMBIOS type 17.
Report
* DIMM size
* channel
* rank per DIMM
* speed in Mhz
* DIMM type
* slot
* manufacturer ID
* serial
Allows dmidecode to print the current RAM configuration.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
* Linux 4.3
* dmidecode 3.0
dmidecode output:
Handle 0x0005, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x0000
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 8 bits
Size: 8192 MB
Form Factor: DIMM
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR3
Type Detail: Synchronous
Speed: 1600 MHz
Manufacturer: Unknown (cd04)
Serial Number: None
Asset Tag: Not Specified
Part Number: F3-1866C9-8GSR
Rank: 2
Configured Clock Speed: 1600 MHz
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
Handle 0x0006, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x0000
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 8 bits
Size: 8192 MB
Form Factor: DIMM
Set: None
Locator: Channel-1-DIMM-1
Bank Locator: BANK 0
Type: DDR3
Type Detail: Synchronous
Speed: 1600 MHz
Manufacturer: Unknown (cd04)
Serial Number: None
Asset Tag: Not Specified
Part Number: F3-1866C9-8GSR
Rank: 2
Configured Clock Speed: 1600 MHz
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
Change-Id: I4e5f772d68484b9cb178ca8a1d63ad99839f3993
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13852
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of hardcoding the maximum supported DDR frequency to
800Mhz (DDR3-1600), read the fuse bits that encode this information.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13487
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The code can't handle cyclic zero runs. Make sure it will never
wrap around by setting the top-most bit to constant one.
Fixes "Mini channel test failed (2)".
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
Change-Id: I55e610d984d564bd4675f9318dead6d6c1e288a3
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13853
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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I first found the missing of #include guards when I tried to include
both sandybridge/gma.h and sandybridge/sandybridge.h, but
sandybridge.h includes gma.h in it and gives a compile error.
Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/13775
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Improved version of
I1a115a45d5febf351d89721ece79eaf43f7ee8a0
The first version wasn't well tested due to the lack of hardware
and it was to aggressive.
With timC being direct function of timB's 6 LSBs it's critical to match
timC and timB.
Some tests increments the value of timB by a small value,
which might cause the 6bit value to overflow, if it's close
to 0x3F.
Increment the value by a small offset if it's likely
to overflow, to make sure it won't overflow while running
tests and bricks the system due to a non matching timC.
In comparission to the first attempt, only 4 out of 128 timB values
are considered bad.
Needs test on real hardware !
Fixes a "edge write discovery failed" on my test system.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Change-Id: If9abfc5f92e20a8f39c6f50cc709ca1cedf6827d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13714
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ib73abb0ada7dfdfab3487c005719e19f51ef1812
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/13779
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Some vendors store lower frequency profiles in the regular SPD,
if the SPD contains a XMP profile. To make use of the board's and DIMM's
maximum supported DRAM frequency, try to parse the XMP profile and
use it instead.
Validate the XMP profile to make sure that the installed DIMM count
per channel is supported and the requested voltage is supported.
To reduce complexity only XMP Profile 1 is read.
Allows my DRAM to run at 800Mhz instead of 666Mhz as encoded in the
default SPD.
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
Change-Id: Ib4dd68debfdcfdce138e813ad5b0e8e2ce3a40b2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13486
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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Use printram() in more places and use printk() only where
it makes sense.
Remove spamming "MRd: %x <= %x\n".
Use common syntax for timing output.
Change-Id: I38965967a029994112d7ab63afd4d9968a7728c5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13414
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Issue observed:
The PCIe Root port shows up in GNU/Linux but no PCIe device
is being detected.
Test system:
* Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)
* Lenovo T530 (Intel Core i5-3320M CPU)
Problem description:
The PEG Root port link training on Ivy Bridge needs to be manually started.
Problem solution:
The bits are set in early_init to meet PCIe reset timeout of 100msec.
The bits should be set in PCI device enable function, but this causes the
PCI enumeration to not detect the card, as it's still booting. Adding
a fixed delay of 100msec resolves this problem, but this would
increase boot time.
Read the PCI base revision mask to make sure it's any IvyBridge CPU.
Don't run the code on MRC path as it has its own PEG initilization code.
Tested with:
* Nvidia NVS 5400M (PCIe2)
* ATI Radeon HD4780 (PCIe2)
* Nvidia GeForce 8600 GT (PCIe1)
Untested:
* PCIe3 devices
Final test results:
The PEG device shows up under GNU/Linux and can be used without issues.
Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/11917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Use shared gpio code from common folder.
Bd82x6x's gpio.c and gpio.h is used by other southbridges
as well and will be removed once it is unused.
Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13614
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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It looks like the falling timing was missing the shift offset.
Not sure if this was intentional, I guess not.
Tested on my hardware and produced no regressions.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Please test on real hardware !
Change-Id: Id8c60217093a48bf322f406ea258c10a02c936e8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13682
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Otherwise the image is simply unusable.
Change-Id: I1e2562ba17279d14dc73b05e4f8fa493e06fbcd2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13699
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Tested by making lenovo x230 configurable despite pretty MRC bugs.
Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13658
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13656
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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We want the question for CBFS size to be next to the rom size in the
mainboard directory, but that doesn't seem to work for how people
want to set the defaults. Instead of having the list of exceptions
to the size, just set the defaults at the end of kconfig.
- Move the defaults for chipsets not setting HAVE_INTEL_FIRMWARE into
the chipset Kconfigs (gm45, nehalem, sandybridge, x4x)
- Override the default for HAVE_INTEL_FIRMWARE on skylake.
- Move the HAVE_INTEL_FIRMWARE default setting into the firmware
Kconfig file
- Move the location of the default CBFS_SIZE=ROM_SIZE to the end of
the top level kconfig file, while leaving the question where it is.
Test=rebuild Kconfig files before and after the change, verify that
they are how they were intended to be.
Note: the Skylake boards actually changed value, because they were
picking up the 0x100000 from HAVE_INTEL_FIRMWARE instead of the
0x200000 desired. This was due to the SOC_INTEL_SKYLAKE being after
the HAVE_INTEL_FIRMWARE default. Affected boards were:
Google chell, glados, & lars and Intel kunimitsu.
Change-Id: I2963a7a7eab037955558d401f5573533674a664f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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In the same time remove few native gfx options which were improperly set
and only added dead code to the binary.
Change-Id: I4ed3fec03a1655ae0a779c3aa3845de273cb12e1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13649
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
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This is needed for stout EC init.
Change-Id: I5c73499c17763229840152a473a2d820802ee2f6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13535
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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This reverts commit 0e06f5bd70b45fd330d8dfb1dc77cce043caf841.
It breaks gm45 and also does some magic without being asked too. It
disables bridge devices permanently if no device was found on the se-
condary bus. In a simple notebook world this might be ok, but it breaks
hot-plugging and late detection (if a secondary bus device comes up too
slow for the firmware to detect and the OS has to enumerate it).
Change-Id: Ia2010640d7c55b0bdd44164b81c75dd4be50410b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/13609
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Walk the bus and try to find enabled devices.
Disable the PEG port if no devices are attached.
Change-Id: I67fcc831fd78ecc6dba83f4e0662ec7549cc2591
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12894
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Issue observed:
The system boots with 4G in channel 0 and 4G in channel 1.
The system doesn't boot with any combination of 4G + 1G in
channel 0 and 4G in channel 1.
In both cases DIMM1 failed, while DIMM0 showed no issues.
Problem description:
The CLK to CMD/CTL was off by a half clock cycle.
The find the issue I X-Y plotted timC vs timB for every
lane on the failing rank.
You can see an offset by 32 units for timB, that is not present on
other ranks.
It turns out that the XOVER CMD/XOVER CTL enable bit for DIMM1 was
missing in program_timings(), which caused the clock offset.
Problem solution:
Add two functions to calculate XOVER CMD and XOVER CTL and use both
to set XOVER in program_timings() and dram_xover().
Final testing result:
The system boots with 4G + 1G in channel 0 and 4G in channel 1.
Test system:
* Intel IvyBridge
* Gigabyte GA-B75M-D3H
Change-Id: I88694c86054ade77e9d8bb2f1fdaf7bc559c1218
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13415
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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It break x230 access to channel 1.
This reverts commit 9f1fbb9a3002e8d74d53d7973bd1c7e3d4879238.
Change-Id: I8a3b13d17729f25cea3460ac2f87bca3c193d388
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13512
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
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Previously with errors in the ram init, early cbmem was disabled.
Now that the ram is working correctly, set as early cbmem platform
and update all (1) boards to use it.
Tested on GA-G41M-ES2L
Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13131
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Tidy up the code and move vga_textmode_init() later
Change-Id: I49967e7197416c955ae6c8775eac7d1a60c92d1c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13128
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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- Fix bug with msbpos, it was not returning the correct result
due to typo in logic, and unsigned value needed to be negative.
- Add reclaim above 4GiB
- Fix to ME related registers near the end of raminit
Change-Id: I04acd0593a457437ee4a42e14b287b2b17a160af
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13127
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
|
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- Add device enable macros
- Set the PMBASE correctly through southbridge device
Change-Id: I1b8cc3de96b1ecaf01e31bad8fba1fada8671c2d
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13126
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Previously, 0xa0000000 to 0xc0000000 needed to be reserved as
a non-usable memory hole because it would hang on memory i/o.
Memtest86+ now passes with no errors on both channels populated.
Tested on GA-G41M-ES2L with 2x2GiB sticks of ram.
Change-Id: Ib52a63a80f5f69c16841f10ddb896ab3c7d30462
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13125
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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VGA grub console works but display wobbles left/right
drm/i915 driver reports one error:
- [drm:i915_irq_handler] *ERROR* pipe A underrun
- Monitor does not display 1920x1080 after modeset
- Other resolutions look out of sync
Cause: suspect single bug in raminit (chipset init)
Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12921
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Linux kernel detects 256 busses but previously only 64 were
allocated. Removes warning in OS.
Change-Id: Id83c85e60025a04acbe6a53dfea6878222d8791f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13033
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
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Change-Id: I0b79ddcf9248c6a6964dd60e30a6ea18e27bc186
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13032
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
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Fixes bug that decode_pciebar() function was bypassed due
to PCI_DEV(0,0,0) being detected as zero and function returning 0.
Change-Id: Ia79bcebbe3ba36f479cbb24dbbb163a031d9c099
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13031
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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This just updates existing guard name comments on the header files
to match the actual #define name.
As a side effect, if there was no newline at the end of these files,
one was added.
Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Count DIMMs on current memory channel instead of all memory channels.
The current code is only able to correctly handle the following memory
configurations:
One DIMM installed in either channel.
Four DIMMs installed, two in each channel.
Two DIMMs installed, both in the same channel.
For systems that have any other configuration the DRAM On-Die-Termination
setting is wrong.
For example:
Two DIMMs installed, one in each channel.
Test system:
* Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)
Change-Id: I0e8e1a47a2c33a326926c6aac1ec4d8ffaf57bb6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
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Register settings are the same as on newer chips (compare sandy-
bridge), just at different locations.
Change-Id: Iea0359165074298a376e0e2ca8f37f71b83ac335
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Skip everything but the final setting of PP_CONTROL, i.e. triggering
the power up. The settings with PANEL_UNLOCK_REGS are useless as no
lockable registers were touched in between. Also the loop waiting for
the panel power up to finish was a no-op as the registers with the
power timings were never filled (see follow-up commits).
Change-Id: Ife27dcafdf197b2246c4e69f2bf7a3a6765d1d82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Remove redundant call to dram_mrscommands().
Change-Id: I157915b4432093c556b538433e3337db1e9c525f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12891
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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- Don't redefine D0F0_PCIEXBAR_LO, use the #define in x4x.h
- Move TPMBASE and TPM32() definitions into iomap.h
- Use "" style include for x4x.h in nortbridge files.
- Move includes of .h files out of x4x.h and into the c files that need
them.
- Protect function definitions in bootblock.
Change-Id: I3fdb579235c5446733a0ffba05fffe1a73381251
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12849
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Change-Id: Ifae3822b6c28832f6aa05a4ffd8f02067a923f2c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12883
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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- occured -> occurred
- accomodate -> accommodate
- existant -> existent
- asssertion -> assertion
- manangement -> management
- cotroller -> controller
Change-Id: Ibd6663752466d691fabbdc216ea05f2b58ac12d1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12850
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Make the low-power and small form factor (SFF) options overridable
from romstage main. Also disable both options by default. That's ok
as there aren't yet any in-tree users of the GS45 chipset. As a nice
side-effect, this adds X200s support to the lenovo/x200 port.
Change-Id: I94373851262e6d424cf4885ceca7260c31bc9f61
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12814
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Passes memtest86+ with either one or two sticks of 2GB ram
but memory map needs a hole at 0xa0000000 to 0xc0000000
Change-Id: Ib34d862cb48b49c054a505fffcba1c17aeb39436
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/11307
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Boots to console on Gigabyte GA-G41M-ES2L
Ram initialization *not* included in this patch
VGA native init works on analog connector
Change-Id: I5262f73fd03d5e5c12e9f11d027bdfbbf0ddde82
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/11305
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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The remainder of the divide operation was being placed into a Local,
but was never being used, causing an IASL warning. Since this
field is optional, just remove the Local.
Fixes IASL warning:
dsdt.aml 640:Divide (Multiply (CTDN, 125), 100, Local0, PL2V)
Warning 3144 - Method Local is set but never used ^ (Local0)
Change-Id: I0b43ef638b1bc3e1163c45f31f8da57aa0d39e22
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12706
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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The ALIGN_CURRENT macro relied on a local variable name
as well as being defined in numerous compilation units.
Replace those instances with an acpi_align_current()
inline function.
Change-Id: Iab453f2eda1addefad8a1c37d265f917bd803202
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12707
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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In coreboot, bool, hex, and int type symbols are ALWAYS defined.
Change-Id: I58a36b37075988bb5ff67ac692c7d93c145b0dbc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12560
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Does native ram init for Intel Atom D5xx 8086:a000 northbridge
Tested on Intel D510MO mainboard, board boots linux kernel
- Works fully with both dimms populated (2x2GB), memtest passes 100%
- Almost boots with only one dimm in one of the slots
(suspect bad memory map with one dimm?)
- Reads garbage with only one dimm in other slot
Change-Id: Ibd22be2a959045e0a83aae2a3a0e877013f80711
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12501
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This patch does *not* include native raminit
Change-Id: I3fb8146ef7fe2ad27c167ecd2fb0fd629f051cc1
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12430
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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Based on i945. Tested on Intel D510MO mainboard,
board boots to UART console with this code.
Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/10073
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Found while doing code review.
Use a function to toggle IO reset signal.
Change-Id: I4cb0885ed9be763fbc4069e4d015a36a7183c823
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/11916
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add lots of comments for better documentation.
Change-Id: Ia203cb649857f979bb6c1c2d405b74f2ccc8f99d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/11915
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
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