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path: root/src/northbridge/intel/sandybridge/raminit_native.c
AgeCommit message (Expand)Author
2022-11-22src/northbridge: Remove unnecessary space after castsElyes Haouas
2022-08-17commonlib/clamp.h: Relicense file to be BSD-compatibleAngel Pons
2021-04-10nb/intel/sandybridge: Use new fixed BAR accessorsAngel Pons
2021-03-01nb/intel/sandybridge: Clean up `dram_timing` functionAngel Pons
2021-02-18nb/intel/sandybridge: Use 133 MHz ref clock for DDR3-2400Angel Pons
2021-02-18nb/intel/sandybridge: Clean up `dram_freq` functionAngel Pons
2020-12-25nb/intel/sandybridge: Move steppings to CPU headerAngel Pons
2020-12-25nb/intel/sandybridge: Rewrite constant valuesAngel Pons
2020-12-23nb/intel/sandybridge: Rename I/O data timingsAngel Pons
2020-11-22nb/intel/sandybridge: Clean up COMPOFST1 logicAngel Pons
2020-11-22nb/intel/sandybridge: Correct get_COMP2 functionAngel Pons
2020-11-22nb/intel/sandybridge: Rename and refactor `discover_timC_write`Angel Pons
2020-11-22nb/intel/sandybridge: Rename and clean up `discover_edges_write`Angel Pons
2020-11-22nb/intel/sandybridge: Run `read_mpr_training` before write trainingAngel Pons
2020-11-22nb/intel/sandybridge: Rename `read_training` functionAngel Pons
2020-11-20nb/intel/sandybridge: Rename `discover_edges` functionsAngel Pons
2020-11-16nb/intel/sandybridge: Drop write_controller_mr() functionAngel Pons
2020-11-16nb/intel/sandybridge: Reduce the scope of get_CWL()Angel Pons
2020-09-21src/northbridge: Drop unneeded empty linesElyes HAOUAS
2020-08-11nb/intel/sandybridge/raminit: Add ECC debug codePatrick Rudolph
2020-07-26nb/intel/sandybridge: Add missing includesElyes HAOUAS
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-19nb/intel/sandybridge: Refactor get_mem_min_tckAngel Pons
2020-04-14nb/intel/sandybridge/raminit: Add ECC supportPatrick Rudolph
2020-03-26nb/intel/sandybridge: Rename raminit_ivy.cAngel Pons
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
2015-07-22intel raminit: rewrite timB high adjust calculationPatrick Rudolph
2015-07-22intel raminit: support two DIMMs per channelPatrick Rudolph
2015-07-13intel raminit: improve loggingPatrick Rudolph
2015-07-13intel raminit: fix timB high adjust calculationPatrick Rudolph
2015-07-13intel raminit: whitespace fixesPatrick Rudolph
2015-07-04intel raminit: rename registerPatrick Rudolph
2015-06-28intel raminit: check correct registers in channel_testPatrick Rudolph
2015-06-28intel raminit: properly handle DDR3 DIMMs with address mirroringPatrick Rudolph
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-02-19sandybridge: Try lower frequency if PLL didn't lock.Vladimir Serbinenko
2015-02-17sandybridge/raminit: Do not die() if timC calibration failsAlexandru Gagniuc
2015-02-15x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointerKevin Paul Herbert
2014-11-30Replace hlt() loops with halt()Patrick Georgi
2014-11-30intel/sandybridge: make sure to stay in HLT until rebootPatrick Georgi
2014-08-25sandybridge: Show spew raminit messages only with raminit debugVladimir Serbinenko
2014-07-29northbridge/intel/sandybridge/raminit_native: Remove stale FIXME.Vladimir Serbinenko
2014-07-29sandy/ivybridge: Native raminit (lint clean)Edward O'Callaghan
2014-07-29sandy/ivybridge: Native raminit.Vladimir Serbinenko
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