diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-11-11 18:49:31 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-16 12:06:44 +0000 |
commit | 2f3cc0035dd29c0d63aa8a32876c84256304b210 (patch) | |
tree | a49b3432b83057d1e3ddecc675d1cd653c8f7b27 /src/northbridge/intel/sandybridge/raminit_native.c | |
parent | 765d465a2358eac0613cf1b2f06cf1fb3434cb09 (diff) |
nb/intel/sandybridge: Reduce the scope of get_CWL()
It is only used once, and can thus be moved to the same file.
Change-Id: I4ee0621449da7fa1970a475d5a2f6e66546357ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_native.c')
-rw-r--r-- | src/northbridge/intel/sandybridge/raminit_native.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 326197b9bd..844e69af3b 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -42,6 +42,41 @@ static u32 get_FRQ(const ramctr_timing *ctrl) die("Unsupported CPU or base frequency."); } +/* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */ +static u8 get_CWL(u32 tCK) +{ + /* Get CWL based on tCK using the following rule */ + switch (tCK) { + case TCK_1333MHZ: + return 12; + + case TCK_1200MHZ: + case TCK_1100MHZ: + return 11; + + case TCK_1066MHZ: + case TCK_1000MHZ: + return 10; + + case TCK_933MHZ: + case TCK_900MHZ: + return 9; + + case TCK_800MHZ: + case TCK_700MHZ: + return 8; + + case TCK_666MHZ: + return 7; + + case TCK_533MHZ: + return 6; + + default: + return 5; + } +} + /* Get REFI based on frequency index, tREFI = 7.8usec */ static u32 get_REFI(u32 FRQ, u8 base_freq) { |