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path: root/src/northbridge/intel/sandybridge/Kconfig
AgeCommit message (Expand)Author
2022-11-04nb/intel/sandybridge: Specify supported memory typesElyes Haouas
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
2021-07-26src/*: Specify type of `CBFS_SIZE` onceAngel Pons
2021-05-05nb/intel: Don't select VBOOT_SEPARATE_VERSTAGEArthur Heymans
2021-02-16vc/google/chromeos: Always use CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
2021-02-16nb,soc/intel: Switch to CHROMEOS_RAMOOPS_DYNAMICKyösti Mälkki
2021-02-10nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
2021-01-30nb/intel/sandybridge: Define and use MMCONF_BUS_NUMBERAngel Pons
2021-01-29device/Kconfig: Declare MMCONF symbols' type onceAngel Pons
2020-12-25nb/intel/sandybridge: Allow to ignore XMP voltageAngel Pons
2020-11-22nb/intel/sandybridge: Refine power-down mode logicAngel Pons
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-14nb/intel/sandybridge/raminit: Add ECC supportPatrick Rudolph
2020-03-25drivers/intel/gma/acpi: Add Kconfigs for backlight registersNico Huber
2020-03-25nb/intel/sandybridge: Use SPDX headersAngel Pons
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-03-02nb/intel/sandybridge: Fix VBOOTPatrick Rudolph
2019-11-26nb/intel/sandybridge: Fix mrc.bin pathArthur Heymans
2019-11-18nb/intel/sandybridge: Move to C_ENVIRONMENT_BOOTBLOCKArthur Heymans
2019-11-18nb/intel/sandybridge: Configure DCACHE_BSP_STACK_SIZEArthur Heymans
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
2019-08-11arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki
2019-06-28{soc,northbridge}/Kconfig: Remove unused CACHE_MRC_SIZE_KBElyes HAOUAS
2019-06-173rdparty/blobs: Update submodule, SNB improvementsArthur Heymans
2019-05-12nb/intel/snb: Drop NORTHBRIDGE_INTEL_IVYBRIDGENico Huber
2019-01-16nb/intel/sandybridge: Remove the C native graphic initArthur Heymans
2018-06-06arch/x86: Make RELOCATABLE_RAMSTAGE the defaultKyösti Mälkki
2018-06-05cpu/intel/model_206ax: Switch to POSTCAR_STAGEArthur Heymans
2018-02-06nb/intel/sandybridge: Always use the same MMCONF_BASE_ADDRESSArthur Heymans
2018-01-26nb/intel/sandybridge: Use common mrc cache functionsArthur Heymans
2017-10-19nb/sandybridge: Add a kconfig option to ignore XMP max DIMMsVagiz Trakhanov
2017-08-11drivers/intel/gma/opregion: migrate from nb/commonMatt DeVillier
2017-08-10nb/intel/sandybridge/raminit: Add Kconfig option for fusesPatrick Rudolph
2017-07-30intel/sandybridge: Gather MMCONF_BASE_ADDRESS defaultsNico Huber
2017-06-15nb/intel/sandybridge/gma: Use common init_igd_opregion methodPatrick Rudolph
2017-06-08device/Kconfig: Put gfx init methods into a `choice`Nico Huber
2017-06-02Kconfig: Introduce HAVE_(VBE_)LINEAR_FRAMEBUFFERNico Huber
2017-06-02Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFGNico Huber
2017-03-28vboot: Select SoC-specific configuration for all Chrome OS boardsJulius Werner
2016-12-07MMCONF_SUPPORT: Flip default to enabledKyösti Mälkki
2016-11-22Remove explicit select MMCONF_SUPPORTKyösti Mälkki
2016-11-18intel/sandybridge post-car: Redo MTRR settings and stack selectionKyösti Mälkki
2016-07-26intel sandy/ivy: Redefine DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZEKyösti Mälkki
2016-06-23intel/sandybridge: Fix builds with System Agent blobKyösti Mälkki
2016-05-31Fix leaking CONFIG_VGA=yKyösti Mälkki
2016-03-11northbridge/intel: move mrccache.c of sandybridge + haswell to commonAlexander Couzens
2016-03-05sandybridge/gma_lvds: support both Sandy&Ivy on one boardIru Cai
2016-02-13sandybridge: Always include MRC if not using native RAM init.Vladimir Serbinenko
2016-02-12Make MRC vs native a config rather than making a separate chipset for it.Vladimir Serbinenko
2016-02-10Kconfig: Move defaults for CBFS_SIZEMartin Roth
2016-02-09sandybridge: Set all native gfx-related options in northbridge code.Vladimir Serbinenko
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
2015-08-25Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in KconfigMartin Roth
2015-06-23Kconfig: Move CBFS_SIZE into Mainboard menuMartin Roth
2015-05-28igd.asl rewriteVladimir Serbinenko
2015-05-26acpi: Remove monolithic ACPIVladimir Serbinenko
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-05-053rdparty: move to 3rdparty/blobsPatrick Georgi
2015-05-053rdparty: Move to blobsPatrick Georgi
2015-01-27CBMEM: Always use DYNAMIC_CBMEMKyösti Mälkki
2014-11-15sandy/ivybridge: Use DYNAMIC_CBMEM with native raminitKyösti Mälkki
2014-10-24sandybridge: Kill CONFIG_HAVE_MRC_CACHEVladimir Serbinenko
2014-09-11Move nehalem/sandy/ivy to per-device acpiVladimir Serbinenko
2014-08-30sandybridge: Add native sandybridgeVladimir Serbinenko
2014-08-25sandybridge: Native gfx init.Vladimir Serbinenko
2014-08-09ivybridge: Don't propose to include systemagent on native boards.Vladimir Serbinenko
2014-07-29ivybridge: LVDS gfx init.Vladimir Serbinenko
2014-07-29sandy/ivybridge: Native raminit.Vladimir Serbinenko
2014-06-25sandy/ivy boards: Switch to use DYNAMIC_CBMEMKyösti Mälkki
2014-01-15sandybridge: Allow skipping mrc.cacheVladimir Serbinenko
2013-08-29Sandybridge/Ivybridge: Unify and fix Kconfig defaultsStefan Reinauer
2013-07-31Drop unused EXTERNAL_MRC_BLOBStefan Reinauer
2013-07-04intel/sandybridge intel/ivybridge: Use MMCONF_SUPPORT_DEFAULTKyösti Mälkki
2013-06-28Add support to enable/disable builtin GbE (again)Stefan Reinauer
2013-06-04Move the MARK_GRAPHICS_MEM_WRCOMB to x86 architectureRonald G. Minnich
2013-03-29sandybridge: add option to mark graphics memory write-combining.Aaron Durbin
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2012-11-17Use new system agent binariesStefan Reinauer
2012-11-09Make coreboot use the offset parameter in cbfstool createStefan Reinauer
2012-11-07SandyBridge/IvyBridge: Use flash map to find MRC cacheStefan Reinauer
2012-07-24Fix MRC cache update delaysStefan Reinauer
2012-05-11Rework Sandybridge MRC cache handlingStefan Reinauer
2012-04-05Add support for Intel Sandybridge CPU (northbridge part)Stefan Reinauer
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