Rework Sandybridge MRC cache handling

- Separate Sandybridge from ChromeOS a bit
  The Sandybridge code depends on chromeos features a whole lot.
  As a first step, provide a code path to look up the MRC cache
  without depending on u-boot.

- Move mrc cache handling to separate file
  This enables us to handle the MRC cache from ramstage,
  where we can write the flash safely (eg. to update the
  cache).
  Also teach it to lookup the current MRC cache from CBMEM,
  as the original data block isn't available anymore.

After all the preparations, finally write to the SPI
as necessary. It's a simple round robin wear levelling
that erases the entire MRC cache region when it's full
and starts from the beginning.

Change-Id: I4751385574cf709b03d5c9d153b7481ffc90ce12
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1001
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 17 insertions, 0 deletions

diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 8cf0a491d6..67b3defb75 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -37,6 +37,23 @@ config CACHE_MRC_SIZE_KB
 	int
 	default 256
 
+# FIXME: build from rom size
+config MRC_CACHE_BASE
+	hex
+	default 0xff800000
+
+config MRC_CACHE_LOCATION
+	hex
+	default 0x1ec000
+
+config MRC_CACHE_SIZE
+	hex
+	default 0x10000
+
+config MRC_CACHE_ALIGNMENT
+	hex
+	default 0x1000
+
 config DCACHE_RAM_BASE
 	hex
 	default 0xff7f0000