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path: root/src/northbridge/intel/ironlake/ironlake.h
AgeCommit message (Expand)Author
2021-04-10nb/intel: Factor out remaining MCHBAR macrosAngel Pons
2021-02-10nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessorsAngel Pons
2021-02-07nb/intel/ironlake: Avoid pointer arithmeticsAngel Pons
2021-01-30nb/intel/ironlake: Use MMCONF_BUS_NUMBER everywhereAngel Pons
2020-12-07nb/intel/ironlake: Introduce memmap.hAngel Pons
2020-12-07nb/intel/ironlake: Drop casts from DEFAULT_{MCHBAR,DMIBAR}Angel Pons
2020-10-13nb/intel/ironlake: Put DMIBAR/EPBAR registers into separate filesAngel Pons
2020-10-10nb/intel/ironlake: Move register headers into a subfolderAngel Pons
2020-10-10nb/intel/ironlake: Clean up DMIBAR/EPBAR registersAngel Pons
2020-09-21src/northbridge: Drop unneeded empty linesElyes HAOUAS
2020-09-17nb/intel/ironlake: Drop invalid `DEFAULT_RCBABASE` macroAngel Pons
2020-08-03nb/intel/ironlake: Add Generic Non-Core register definitionsAngel Pons
2020-08-03nb/intel/ironlake: Add Generic Non-Core PCI device definitionAngel Pons
2020-08-03nb/intel/ironlake: Add QPI Physical Layer registersAngel Pons
2020-08-03nb/intel/ironlake: Add QPI Physical Layer device definitionAngel Pons
2020-08-03nb/intel/ironlake: Add QPI Link register definitionsAngel Pons
2020-08-03nb/intel/ironlake: Add definition for QPI Link PCI deviceAngel Pons
2020-08-03nb/intel/ironlake: Add SAD DRAM register definitionsAngel Pons
2020-08-03nb/intel/ironlake: Correct PCIEXBAR definitionAngel Pons
2020-08-03nb/intel/ironlake: Add definition for SAD PCI deviceAngel Pons
2020-08-03nb/intel/ironlake: Put host bridge registers into its own fileAngel Pons
2020-07-01nb/intel/ironlake/ironlake.h: Clean upAngel Pons
2020-07-01nb/intel/ironlake: Remove unused structsAngel Pons
2020-05-11treewide: Remove "this file is part of" linesPatrick Georgi
2020-04-05src/northbridge: Use SPDX for GPL-2.0-only filesAngel Pons
2020-03-17src (minus soc and mainboard): Remove copyright noticesPatrick Georgi
2020-03-15nb/intel/nehalem: Rename to ironlakeAngel Pons