diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 18:17:33 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:31:59 +0000 |
| commit | a457e352374e0efe4944bd1c81a3ca8ffd65b750 (patch) | |
| tree | aaec60fd63129b58bc974f6144bd172766d2de1d /src/northbridge/intel/ironlake/ironlake.h | |
| parent | 10993c4ad40c92b2b2796856f9de2a5f602a2da9 (diff) | |
nb/intel/ironlake: Add QPI Physical Layer registers
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I44db564c757647f493e92d35602178ef8b722517
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/ironlake/ironlake.h')
| -rw-r--r-- | src/northbridge/intel/ironlake/ironlake.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index d09ccccfd7..06e07716e9 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -75,6 +75,16 @@ */ #define QPI_PHY_0 PCI_DEV(QUICKPATH_BUS, 2, 1) +#define QPI_PLL_STATUS 0x50 +#define QPI_PLL_RATIO 0x54 +#define QPI_PHY_CAPABILITY 0x68 /* QPI Phys. Layer Capability */ +#define QPI_PHY_CONTROL 0x6c /* QPI Phys. Layer Control */ +#define QPI_PHY_INIT_STATUS 0x80 /* QPI Phys. Layer Initialization Status */ +#define QPI_PHY_PRIM_TIMEOUT 0x94 /* QPI Phys. Layer Primary Timeout Value */ +#define QPI_PHY_PWR_MGMT 0xd0 /* QPI Phys. Layer Power Management */ +#define QPI_PHY_EP_SELECT 0xe0 /* QPI Phys. Layer Electrical Parameter Select */ +#define QPI_PHY_EP_MCTR 0xf4 /* QPI Phys. Layer Electrical Parameter Misc. Control */ + /* Device 0:2.0 PCI configuration space (Graphics Device) */ |