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authorAngel Pons <th3fanbus@gmail.com>2020-07-22 18:21:43 +0200
committerPatrick Georgi <pgeorgi@google.com>2020-08-03 05:32:12 +0000
commitc642a0d8942735b393040b877769f1d4a3a9ebe8 (patch)
treecf118ea9fd286c47bed111a309f23e47c99cba65 /src/northbridge/intel/ironlake/ironlake.h
parenta457e352374e0efe4944bd1c81a3ca8ffd65b750 (diff)
nb/intel/ironlake: Add Generic Non-Core PCI device definition
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change. Change-Id: I8feff0d71ad70ac994e29b238d35e2c73aa92ecd Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/ironlake/ironlake.h')
-rw-r--r--src/northbridge/intel/ironlake/ironlake.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index 06e07716e9..4f9db5b347 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -48,6 +48,11 @@
#include "hostbridge_regs.h"
/*
+ * Generic Non-Core Registers
+ */
+#define QPI_NON_CORE PCI_DEV(QUICKPATH_BUS, 0, 0)
+
+/*
* SAD - System Address Decoder
*/
#define QPI_SAD PCI_DEV(QUICKPATH_BUS, 0, 1)