aboutsummaryrefslogtreecommitdiff
path: root/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
AgeCommit message (Expand)Author
2019-11-20nb/amd/fam10: Drop supportArthur Heymans
2019-08-20src: Remove variable length arraysJacob Garber
2019-08-10src: Include <stdint.h> instead of <inttypes.h>Jacob Garber
2019-07-02src: Use CRx_TYPE type for CRxElyes HAOUAS
2018-11-12src: Remove unneeded include "{arch,cpu}/cpu.h"Elyes HAOUAS
2018-11-05amd/mtrr: Fix IORR MTRRElyes HAOUAS
2018-10-30{cpu,drivers,nb,sb}/amd: Replace {MSR,MTRR} addresses with macrosElyes HAOUAS
2018-10-18cpu/amd: Use common AMD's MSRElyes HAOUAS
2018-07-09src/northbridge: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
2018-06-14src: Get rid of unneeded whitespaceElyes HAOUAS
2018-05-09{device,drivers,lib,mb,nb}: Use only one space after 'if'Elyes HAOUAS
2017-01-11amd/mct/ddr3: Avoid using uninitialized register address in ECC setupTimothy Pearson
2017-01-10amd/mct/ddr3: Fix incorrect DQ mask calculationTimothy Pearson
2017-01-10amd/mct/ddr2|ddr3: Refactor persistent members of DCTStatStrucTimothy Pearson
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
2016-09-21northbridge/amd/amdmct: Improve code formattingElyes HAOUAS
2016-08-31northbridge/amd: Add required space before opening parenthesis '('Elyes HAOUAS
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
2016-05-09nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15hTimothy Pearson
2016-05-01nb/amd/mct_ddr3: Stop receiver enable cycle training after window foundTimothy Pearson
2016-05-01nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0Timothy Pearson
2016-03-26nb/amd/amdmct: Select max_lanes based on ECC presence or absenceDamien Zammit
2016-03-24nb/amd/mct_ddr3: Set the NBP0 read latency from P0 trained valuesTimothy Pearson
2016-03-21nb/amd/amdmct/mct_ddr3: Ensure BlockRxDqsLock does not remain setTimothy Pearson
2016-03-13nb/amd/mct_ddr3: Use correct initial UI setting during DRAM trainingTimothy Pearson
2016-03-12nb/amd/mct_ddr3: Consolidate duplicated codeTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Train correct receiver in TrainDQSRdWrPos_D_Fam15Timothy Pearson
2016-03-11nb/amd/mct_ddr3: Require minumum training quality for both read and writeTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Set read DQS delay to 1UI before calculating read latencyTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Properly initialize arrays and add bounds checksTimothy Pearson
2016-03-11nb/amd/mct_ddr3: Restore previous DQS delay values on failed loopTimothy Pearson
2016-02-05nb/amd/mct_ddr3: Work around RDIMM training failureTimothy Pearson
2016-01-24nb/amd/mct_ddr3: Add additional verbose-level debug statementsTimothy Pearson
2015-12-01nb/amd/mct_ddr3: Add Family 15h tristate enable codesTimothy Pearson
2015-11-30nb/amd/amdmct/mct_ddr3: Use StopOnError to decrease training timeTimothy Pearson
2015-11-30nb/amd/mct_ddr3: Use antiphase to better center DQS windowTimothy Pearson
2015-11-29nb/amd/mct_ddr3: Fix odd rank data corruptionTimothy Pearson
2015-11-23amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUsTimothy Pearson
2015-11-16northbridge/amd/mct_ddr3: Add registered and x4 DIMM support to Fam15hTimothy Pearson
2015-11-16amd/amdmct/mct_ddr3: Partially fix up registered DIMMs on Fam10hTimothy Pearson
2015-11-15cpu/amd: Fix AMD Family 15h ECC initialization reliability issuesTimothy Pearson
2015-11-02cpu/amd: Add initial AMD Family 15h supportTimothy Pearson
2015-10-31tree: drop last paragraph of GPL copyright headerPatrick Georgi
2015-10-26northbridge/amd/amdmct: Fix broken AMD K10 DDR3 memory initalizationTimothy Pearson
2015-05-21Remove address from GPLv2 headersPatrick Georgi
2015-01-06northbridge: Drop print_ implementation from non-romcc boardsStefan Reinauer
2014-07-29Uniformly spell frequency unit symbol as HzElyes HAOUAS
2013-06-03northbridge/amd/amdmct: Use `static const` instead of `const static`Paul Menzel
2013-03-01GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«Paul Menzel
2011-10-15AMD CPU and chipset fixes for compilation with gcc 4.6Stefan Reinauer
2011-01-06Fix some settings fo AMD MCT. It is based on BIOS test suite.Zheng Bao
2010-10-13Trivial. Clean up code and add some comments.Zheng Bao
2010-10-08Trivial. Spell checking.Zheng Bao
2010-08-30Multi-DIMMS on AMD ddr3 MCT channel B works.Kerry She
2010-04-23DDR3 support for AMD Fam10.Zheng Bao
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-03 10:28:10 +0000