northbridge/amd/amdmct: Improve code formatting

Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

1 files changed, 22 insertions, 22 deletions

diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 06a70e6ebb..71a4b79424 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -247,12 +247,12 @@ static void SetEccDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
 	u8 channel;
 	u8 direction;
 
-	for (channel = 0; channel < 2; channel++){
+	for (channel = 0; channel < 2; channel++) {
 		for (direction = 0; direction < 2; direction++) {
 			pDCTstat->Channel = channel;	/* Channel A or B */
 			pDCTstat->Direction = direction; /* Read or write */
 			CalcEccDQSPos_D(pMCTstat, pDCTstat, pDCTstat->CH_EccDQSLike[channel], pDCTstat->CH_EccDQSScale[channel], ChipSel);
-			print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction==DQS_READDIR? " R dqs_delay":" W dqs_delay",	pDCTstat->DQSDelay, 2);
+			print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction == DQS_READDIR? " R dqs_delay":" W dqs_delay",	pDCTstat->DQSDelay, 2);
 			pDCTstat->ByteLane = 8;
 			StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel);
 			mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel);
@@ -294,7 +294,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
 		GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel);
 		DQSDelay1 = pDCTstat->DQSDelay;
 
-		if (DQSDelay0>DQSDelay1) {
+		if (DQSDelay0 > DQSDelay1) {
 			DQSDelay = DQSDelay0 - DQSDelay1;
 		} else {
 			DQSDelay = DQSDelay1 - DQSDelay0;
@@ -306,7 +306,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
 
 		DQSDelay >>= 8;		/* 256 */
 
-		if (DQSDelay0>DQSDelay1) {
+		if (DQSDelay0 > DQSDelay1) {
 			DQSDelay = DQSDelay1 - DQSDelay;
 		} else {
 			DQSDelay += DQSDelay1;
@@ -493,7 +493,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
 			}
 
 			print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 14 TestAddr ", TestAddr, 4);
-			SetUpperFSbase(TestAddr);	/* fs:eax=far ptr to target */
+			SetUpperFSbase(TestAddr);	/* fs:eax = far ptr to target */
 
 			print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 12 Receiver ", Receiver, 2);
 
@@ -556,7 +556,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
 						ResetTargetWTIO_D();
 
 						/* Read and compare pattern */
-						bytelane_test_results &= (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0=fail, 1=pass */
+						bytelane_test_results &= (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */
 
 						/* If all lanes have already failed testing bypass remaining re-read attempt(s) */
 						if (bytelane_test_results == 0x0)
@@ -650,7 +650,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
 				ResetTargetWTIO_D();
 
 				/* Read and compare pattern from the base test address */
-				bytelane_test_results = (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0=fail, 1=pass */
+				bytelane_test_results = (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */
 
 				/* Store any lanes that passed testing for later use */
 				for (lane = 0; lane < 8; lane++)
@@ -814,7 +814,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
 				for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) {
 					printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD);
 					p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir];
-					for (i=0;i<8; i++) {
+					for (i = 0; i < 8; i++) {
 						val  = p[i];
 						printk(BIOS_DEBUG, " %02x", val);
 					}
@@ -834,7 +834,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
 		lo &= ~(1<<17);		/* restore HWCR.wrap32dis */
 		_WRMSR(addr, lo, hi);
 	}
-	if (!_SSE2){
+	if (!_SSE2) {
 		cr4 = read_cr4();
 		cr4 &= ~(1<<9);		/* restore cr4.OSFXSR */
 		write_cr4(cr4);
@@ -1583,7 +1583,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
 					for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) {
 						printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD);
 						p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir];
-						for (i=0;i<8; i++) {
+						for (i = 0; i < 8; i++) {
 							val  = p[i];
 							printk(BIOS_DEBUG, " %02x", val);
 						}
@@ -1843,7 +1843,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
 				for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) {
 					printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD);
 					p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir];
-					for (i=0;i<8; i++) {
+					for (i = 0; i < 8; i++) {
 						val  = p[i];
 						printk(BIOS_DEBUG, " %02x", val);
 					}
@@ -1863,7 +1863,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
 		lo &= ~(1<<17);		/* restore HWCR.wrap32dis */
 		_WRMSR(addr, lo, hi);
 	}
-	if (!_SSE2){
+	if (!_SSE2) {
 		cr4 = read_cr4();
 		cr4 &= ~(1<<9);		/* restore cr4.OSFXSR */
 		write_cr4(cr4);
@@ -1890,11 +1890,11 @@ static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat,
 	buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0));
 	if (pDCTstat->Status & (1<<SB_128bitmode)) {
 		pDCTstat->Pattern = 1;	/* 18 cache lines, alternating qwords */
-		for (i=0; i<16*18; i++)
+		for (i = 0; i < 16*18; i++)
 			buf[i] = TestPatternJD1b_D[i];
 	} else {
 		pDCTstat->Pattern = 0;	/* 9 cache lines, sequential qwords */
-		for (i=0; i<16*9; i++)
+		for (i = 0; i < 16*9; i++)
 			buf[i] = TestPatternJD1a_D[i];
 	}
 	pDCTstat->PtrPatternBufA = (u32)buf;
@@ -1966,10 +1966,10 @@ static u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat,
 	else
 		dct = 0;
 
-	if (ChipSel < MAX_CS_SUPPORTED){
+	if (ChipSel < MAX_CS_SUPPORTED) {
 		reg = 0x40 + (ChipSel << 2);
 		val = Get_NB32_DCT(dev, dct, reg);
-		if (val & ( 1 << 0))
+		if (val & (1 << 0))
 			ret = 1;
 	}
 
@@ -2058,7 +2058,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat
 	}
 
 	bytelane = 0;		/* bytelane counter */
-	bitmap = 0xFFFF;	/* bytelane test bitmap, 1=pass */
+	bitmap = 0xFFFF;	/* bytelane test bitmap, 1 = pass */
 	MEn1Results = 0xFFFF;
 	BeatCnt = 0;
 	for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */
@@ -2102,7 +2102,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat
 		if (!bitmap)
 			break;
 
-		if (bytelane == 0){
+		if (bytelane == 0) {
 			BeatCnt += 4;
 			if (!(pDCTstat->Status & (1 << SB_128bitmode))) {
 				if (BeatCnt == 8) BeatCnt = 0; /* 8 beat burst */
@@ -2132,7 +2132,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat,
 					u32 addr_lo)
 {
 	/* Flush functions in mct_gcc.h */
-	if (pDCTstat->Pattern == 0){
+	if (pDCTstat->Pattern == 0) {
 		FlushDQSTestPattern_L9(addr_lo);
 	} else {
 		FlushDQSTestPattern_L18(addr_lo);
@@ -2349,9 +2349,9 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat,
 
 	val &= ~0xe007c01f;
 
-	/* unganged mode DCT0+DCT1, sys addr of DCT1=node
+	/* unganged mode DCT0+DCT1, sys addr of DCT1 = node
 	 * base+DctSelBaseAddr+local ca base*/
-	if ((Channel) && (pDCTstat->GangedMode == 0) && ( pDCTstat->DIMMValidDCT[0] > 0)) {
+	if ((Channel) && (pDCTstat->GangedMode == 0) && (pDCTstat->DIMMValidDCT[0] > 0)) {
 		reg = 0x110;
 		dword = Get_NB32(dev, reg);
 		dword &= 0xfffff800;
@@ -2365,7 +2365,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat,
 			val += dword;
 		}
 	} else {
-		/* sys addr=node base+local cs base */
+		/* sys addr = node base+local cs base */
 		val += pDCTstat->DCTSysBase;
 
 		/* New stuff */