diff options
| author | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-05-07 16:05:05 -0500 |
|---|---|---|
| committer | Timothy Pearson <tpearson@raptorengineeringinc.com> | 2016-05-09 20:43:29 +0200 |
| commit | d112f46bed85dcd6d064a057c2d355d68559f780 (patch) | |
| tree | 249b90bec4a00a2d1e1a6acb27544334fb1dba7b /src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | |
| parent | 12a8aba4189d1f628a481942b08275503837dd88 (diff) | |
nb/amd/mct_ddr3: Add support for non-ECC DIMMs on AMD Family 15h
While some stubs existed before this patch to handle non-ECC
memory initialization, there were a number of ECC detect unaware
sections of code. Add ECC support detection to those sections.
Change-Id: I56dad8a0f6833b2f42796212afb9777e9cc73d6d
Tested-On: ASUS KGPE-D16
Tested-With: 1x Opteron 6262
Tested-With: 1x SuperTalent 4G non-ECC DIMM in slot A2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/14737
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c')
| -rw-r--r-- | src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 69a5fe3fe0..2501410985 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 - 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -1085,7 +1085,10 @@ static void read_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x274, ~0xffffffff); Set_NB32_DCT(dev, dct, 0x278, ~0xffffffff); dword = Get_NB32_DCT(dev, dct, 0x27c); - dword &= ~(0xff); /* EccMask = 0x0 */ + if (get_available_lane_count(pMCTstat, pDCTstat) < 9) + dword |= 0xff; /* EccMask = 0xff */ + else + dword &= ~(0xff); /* EccMask = 0x0 */ Set_NB32_DCT(dev, dct, 0x27c, dword); } else { Set_NB32_DCT(dev, dct, 0x274, ~0x0); @@ -1178,7 +1181,10 @@ static void write_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x274, ~0xffffffff); Set_NB32_DCT(dev, dct, 0x278, ~0xffffffff); dword = Get_NB32_DCT(dev, dct, 0x27c); - dword &= ~(0xff); /* EccMask = 0x0 */ + if (get_available_lane_count(pMCTstat, pDCTstat) < 9) + dword |= 0xff; /* EccMask = 0xff */ + else + dword &= ~(0xff); /* EccMask = 0x0 */ Set_NB32_DCT(dev, dct, 0x27c, dword); } else { Set_NB32_DCT(dev, dct, 0x274, ~0x0); @@ -1790,7 +1796,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8), dword); } - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < lane_count; lane++) { if (!lane_training_success[lane]) { dct_training_success = 0; Errors |= 1 << SB_NODQSPOS; |