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The Nuvoton EC requires a window to be opened for updates, so open
this window only if the Nuvoton EC is present.
Change-Id: Iaa45aa58749c4d0bfc77e60b52eab2bcb270f3ee
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib5fec81a7a04f2f5ab13784435944601902904d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie9bc6b3e20dddeb14cea195ef9a719432f66c6e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I47523fae8d1cb0fbb972a82c43a992c9fb606ed4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2d949af0086c231e27ac889c0aabd0d3e00c94fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add support for the MT53E2G32D4NQ-046 WT:C and MT53E512M32D1NP-046 WT:B
memory parts to skolas4es.
BUG=b:236284219
BRANCH=firmware-brya-14505.B
TEST=None
Change-Id: I5e3534985e12535ccc4285a0d829bca04781cf1b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65179
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Update Shotzo own ec.h with the battery, lid and ps2
defines stripped.
This is to ensure the correct ASL is generated so that we don't
advertise PS2 keyboard support and battery/lid interrupts which
don't exist.
In MAINBOARD_EC_SCI_EVENTS drop following events.
EC_HOST_EVENT_LID_OPEN
EC_HOST_EVENT_LID_CLOSED
EC_HOST_EVENT_BATTERY_LOW
EC_HOST_EVENT_BATTERY_CRITICAL
EC_HOST_EVENT_BATTERY
EC_HOST_EVENT_BATTERY_STATUS
set MAINBOARD_EC_SMI_EVENTS to 0 and drop
EC_HOST_EVENT_LID_CLOSED smi event.
In MAINBOARD_EC_S5_WAKE_EVENTS drop below event.
EC_HOST_EVENT_LID_OPEN
In MAINBOARD_EC_S3_WAKE_EVENTS drop following events.
EC_HOST_EVENT_AC_CONNECTED
EC_HOST_EVENT_AC_DISCONNECTED
EC_HOST_EVENT_KEY_PRESSED
EC_HOST_EVENT_KEY_PRESSED
BUG=b:235303242
BRANCH=dedede
TEST=Build
Change-Id: I5717e2e8ca7549d160fe46ccde31c6d7cf9649d7
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65167
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The EEs and I misunderstood, and apparently the vfio-pci kernel driver
will turn off the dGPU when it sees it is unused, so coreboot should
leave the dGPU on so the kernel driver can save state before it shuts it
down.
TEST=Tested by ODM
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I30b5dead7a5302f3385ddcaecfbf134c3bb68779
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65181
Reviewed-by: Robert Zieba <robertzieba@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Update PL1 and PL2 based on the suggestion of the thermal team.
Then the settings are both updated in firmware log.
BUG=b:233703656, b:233703655
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ibb81a1a8519b88ed4774385d9ccf895d64bbdc21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Create the joxer variant of the nissa reference board by copying
the template files to a new directory named for the variant.
BUG=b:236086879
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_JOXER
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I4cb74f90c4ec33818b551d5f51759930e3222677
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
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Add pujjo supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K3LKBKB0BM-MGCP, K3LKCKC0BM-MGCP
2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6E
3. Micron MT62F512M32D2DR-031 WT:B
BUG=b:235765890
TEST=Use part_id_gen to generate related settings
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I929527a219452082e416803f7a74d470be5a188c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65100
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, the system fails to enter S0ix as the stop pin declation
for LAN device will prevent system from entering suspend.
So remove the stop pin declaration.
Also add device_index=0 for the first NIC to get correct MAC
from VPD setting.
BUG=b:210970640
TEST=Build and suspend_stress_test -c 20 pass
Check LAN works fine after resume
Change-Id: I513bf8b4bcb4d6db2eed2790fef7f6000a441274
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65123
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The two HDMI ports on x9sae(-v) prove to be wired to HDMI2 and HDMI3.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: I07870fd70612c9ed01a833f173b18053807ad2b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Add Elan touchscreen support for craaskvin.
BUG=b:235919755
TEST=Build and test on MB, touchscreen function works.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I18e0be688705942647c42ee532fcd32e862fe78c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Add ALC5682I-VS related settings. And add codec/amplifier space in
fw_config.
BUG=b:229048361, b:235436515
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I567d3567318c810e19ae9e9ba5e0dc8332517866
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Use fw_config Bit 5 to control whether to disable SD card:
Bit 5 = 0 --> enable SD card
Bit 5 = 1 --> disable SD card
BUG=b:229048361
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ib5e92600564e2138e32a0d2e60259b9767516a4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65129
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update gpio configuration based on GPIO_0610b.xlsx.
BUG=b:226182106, b:226182090
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=banshee emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I2b447629645690e5e97a17fff25860838f4f3344
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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CPU_SAMSUNG_EXYNOS5420 has its own boot device implementation
(src/soc/samsung/exynos5420/alternate_cbfs.c), so
BOOT_DEVICE_NOT_SPI_FLASH should be selected.
Change-Id: I0a9f96ad68b28773ede4e99510bd33867789e185
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65109
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Different board versions have different audio layouts, therefore
support both layouts by enabling only the appropriate devices
in the devicetree via board_id().
BUG=b:207333035
BRANCH=none
TEST='FW_NAME=vell emerge-brya coreboot'
Change-Id: If053b8f85933f8fc75589ae175e225cc9c1e3991
Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65124
Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM
features from RTD3.
PCIe root port: 6 (1 based)
clock source & request: 5 (0 based)
GPIOs:
WWAN_PERST_N: GPPC_C5
WWAN_RST_N: GPPC_F14
WWAN_FCP_OFF_N: GPPC_F15
WWAN_WAKE_N: GPPC_D18
WWAN_PWREN: GPPC_F21
WWAN_DISABLE_N: GPPC_D15
CLKREQ5_WWAN_N: GPPC_H23
TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3
are generated under the root port.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I10902245e3a5e05cd2af9030394933e936c25396
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63941
Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
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Some SKUs of crota have VNN 1.05v bypass rails for additional
power savings in S0ix states. This patch uses FW_CONFIG to enable
that feature when run on the applicable SKUs.
BUG=b:233175019
BRANCH=none
TEST=emerge-brya coreboot and verified pass
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Iaade50f4fe821b7114b3e2d44bda0747816da11c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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enable_cnvi_ddr_rfim enables DDR RFI mitigation feature, this feature
needs to be enabled for all brya variants. Currently, it's not enabled
for brya4es.
BUG=b:201724512
TEST=Build, boot brya4es and check function 3 in _DSM method under
\_SB.PCI0.WFA3
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I6cc9d3e4721188dcbc8584596c9f3f89a737206f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65110
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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- Set the speed to I2C_SPEED_FAST in each speed_config so that the
speed_config is actually applied. Currently, the speed_config isn't
applied, so the hcnt/lcnt calculation falls back to rise_time_ns and
fall_time_ns, which are 0 since they're not set. This results in
frequencies around 300 kHz.
- Move the data hold time to the speed_config, ensuring that the
resulting sda_hold value remains the same.
- For nivviks and nereid, tune scl_lcnt and scl_hcnt for each bus to
give a frequency around 390 kHz.
- In the baseboard, keep default scl_lcnt and scl_hcnt values. These
work well for buses with a rise time around 100 ns, and can be used as
a starting point before tuning them for a specific variant.
BUG=b:229547183
TEST=Measure the clock frequency, tHIGH, tLOW and tVD;DAT on nivviks
and nereid and check they meet the spec.
nereid clock frequencies:
I2C0 - 387.9 kHz
I2C1 - 392.7 kHz
I2C3 - 386.3 kHz
I2C5 - 383.6 kHz
nivviks clock frequencies:
I2C0 - 387.67 kHz
I2C1 - 380.47 kHz
I2C2 - 388.51 kHz
I2C3 - 384.03 kHz
I2C5 - 389.09 kHz
Change-Id: I88a6cfcc893183385eb85a89489e5d270277e537
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64942
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
- MT53E512M32D2NP-046 WT:E
- H9HCNNNBKMMLXR-NEE
- K4U6E3S4AA-MGCR
- MT53E512M32D1NP-046 WT:B
- H54G46CYRBX267
- K4U6E3S4AB-MGCL
- K4U6E3S4AA-MGCL
BUG=b:235303242
BRANCH=dedede
TEST=build
Change-Id: Ie0ffdfed47b1791b990affd9eee262faede4b0c8
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65081
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
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Introduce a new field in the board settings EEPROM region to control
whether BIOS menu is to be enabled. This field will be used in EDK2
payload.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I0af81c9e70a0088caea6bc7e2b81eab9a123c0f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
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+----------------+
A2 | | A0
C2 | | C0
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+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I8cc7be20988ff3cc3be1fac3c9b143059ff9190c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65088
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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change clk_src and clk_req to 4 for LAN_I225V based on
ADL_Moli_SC_MB_20220601.pdf.
BUG=b:235768639
TEST=emerge-brask coreboot and check LAN_I225V can connect.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I323726df84d07703402da9da44b1882a0cdc1e33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Remove the cnvi_bt_audio_offload because it is already probed in
variant.c for moli.
BUG=b:235426221
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I15077ca161b6283e764105d1c2fbc59ead1fd761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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enable use_custom_pld to match the custom physical location define.
BUG=b:235426221
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I62d133eed02faf4e5ad054a0901f73b1196c4c6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Won Chung <wonchung@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Apparently all nine HP Sandy/Ivy laptop variants select
MAINBOARD_USES_IFD_GBE_REGION. So let's move it to the COMMON section.
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: I48e0d03c59d3ba013b479b59df8a15a0f8d23c50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65115
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Currently, ADL FSP headers and RPL FSP headers differ. Set a RPL only
upd for adlrvp with Raptor Lake silicon. This code can be removed once
ADL and RPL start using the same FSP.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I4e69323949233aa8c325a757b28b9d80cbdf4322
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia24a502994d24f3341273c5e6f768687ad20baf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65113
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The general purpose PCIe clock outputs 0, 1 and 3 are used with their
corresponding clock request pins, so set the gpp_clk_config to
GPP_CLK_REQ for those and disable the unused output 2. This matches the
DXIO descriptor in port_descriptors.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38ab8d6d824617509fdd18f06d5593889ec50666
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65112
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change fixes wrong type-C port number for voxel. Voxel
uses tcss_usb3_port1 not tcss_usb3_port3.
BUG=b:231344977
BRANCH=volteer
TEST=Check the transactions are happening on correct port. Also checked
retimer firmware update on both the ports.
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Change-Id: Iba7b3b15296bed99d3626a6d53dfd59e8d20fe5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64022
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update SoC GPIO setting of unused I2C camera pins according to beadrix
schematics.
GPP_H6 : NF1 -> NC (AP_I2C_CAM_SDA)
GPP_H7 : NF1 -> NC (AP_I2C_CAM_SCL)
BRANCH=dedede
BUG=b:235005592
TEST=on beadrix, validated by beadrix's camera still working properly.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I8be57406a44096c764c1faa8f45267d08c4694fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64971
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Update FW_CONFIG probe for daughter board LTE and mainboard SAR
according to beadrix schematics.
BRANCH=dedede
BUG=b:226910787, b:213549229, b:233983127
TEST=on beadrix, validated by beadrix LTE working properly.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I126a1c548b6314acc0749fcfbdffd8f482c4f46c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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The APOB data in DRAM is larger than the 96 kBytes of RW_MRC_CACHE, so
it won't fit in the flash and makes soc_update_apob_cache return early
before writing the APOB data from DRAM into the flash with this warning:
[WARN ] RAM APOB data is too large 1db18 > 18000
Increasing the RW_MRC_CACHE size to 120 kByte fixes this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I763d20f504d4f5b7cea68f21f409de9a1035f440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64555
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The T6 of PS8640 power on sequence should be larger than 0ms, but it's
-0.062ms now. Add 100us delay between VRF12 and VCN33. The PS8640
power-on sequence is described in the "PS8640_DS_V1.4_20200210.docx".
BUG=b:235448279
BRANCH=None
TEST=The sequence T6 is larger than 0ms when power on.
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I0b8a37d6119dc027a9d1c0a62c087b0a7ef14cac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
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The TBT device can't be recognized after we re-plug it at DB type-c
port. Intel found that tbt_pcie_rp0 has mapping error after each
re-plug. From Intel suggestion, we enable TBT PCIe RP0 to fix this
problem and take this as short term solution. Intel will implement
re-mapping mechanism in ACPI for long term solution.
BUG=b:230141802
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I61429033dfe64d67916167bb901bdd8246db953e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Add FM350GL 5G WWAN support using drivers/wwan/fm and additional PM
features from RTD3.
TEST=Check SSDT table to see if the PXSX device and PowerResource RTD3
are generated under the root port.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I74434d833086f639927d8369f8a6e3af31dd99e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64648
Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
BUG=b:229134437
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Ib0531ff736ed7ac52bff8607b26b3e7f1d3ac3ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I12eab0fe2a3c21011f50c72718514fbc90cbe658
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Set the MS bit in EC SW02 register to enable s0i3
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I97b6adf48b49635251c70015f1d87fd8ca11d539
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
1. enable DDI_PORT_1, DDI_PORT_3 hot plug detection to let
tcp0 and tcp2 can display
2. remove DDI_ENABLE_DDC for Port 2, because tcp-dp dosen't need to
enable DDC
BUG=b:234521799
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I1354b82d881ebd838c310b32ae28ac2628ab8c9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable USB retimer in moli overridetree.
BUG=b:233869074
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ib7ea0b0d85776857d07e129935059397720fa0e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
In Adl-P RVP, those interfaces are used as USB ports.
BRANCH=firmware-brya-14505.B
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I322280ab02361e3a2a5925d69f33b23453d36dbf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63946
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Use clock src and clock req to 7 for x4 slot.
Remove free running clock setting for clock 6.
Configure gpio for source clock OEB native function going to x4 slot.
BUG=b:233252409
BRANCH=firmware-brya-14505.B
TEST=insert SD AIC to x4 slot. boot to OS and use 'lspci' to check
the device.
ex:
58:00.0 SD Host controller: O2 Micro, Inc. Device 8621 (rev 01)
NOTE: The bus number varies.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: Iba5d83d133b6ae8cd389ddd971db308170094300
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
|
|
When the CMOS option `power_profile` is set to Power Saver, disable
Burst.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4d9367306b3c0e83252cea3ee4c2733c8729d10c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Shotzo is not a laptop (it is a Chromebase), therefore deselect
BASEBOARD_DEDEDE_LAPTOP.
BUG=b:235303242
BRANCH=dedede
TEST=build
Change-Id: I4669ef163e4bd8f2de556a051197802ee2d54927
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65015
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create the shotzo variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.).
BUG=b:235303242
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_SHOTZO
Change-Id: Ia3dc9ea6d1b369b54a966ad86f1531305b8a7f57
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65014
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
|
|
mainboard_vbt_filename() is to decide which VBT to return,
but moli only has one VBT, so it doesn't need this function.
BUG=b:234521809
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ia9c1495c8cb7bf7b47d9c616891a791a32b9d805
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64848
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Create new variant of Brya "ghost4adl".
Memory config and device tree was sourced from the schematics
(revision 7670d041f40279b5126990f20ec8f90c0538440c).
GPIO overrides have not been added yet. This is to be added in a
follow-on CL.
BUG=b:234626939
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=ghost4adl emerge-brya chromeos-bootimage
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I43c663d700ce8b53248fe203f0becc52610ddb70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
|
|
Override the type-C USB2 port setting from `USB2_PORT_TYPE_C` to `USB2_PORT_MAX_TYPE_C`.
The change is required to detect USB2 device on type-C port of Agah boards.
BUG=b:233554817
TEST=build and test USB2 hub could be detected on both the Type-C ports.
=================================================================
usb 3-3: New USB device found,idVendor=1a40,idProduct=0801,bcdDevice= 1.00
usb 3-3: New USB device strings: Mfr=0, Product=1, SerialNumber=0
usb 3-3: Product: USB 2.0 Hub
hub 3-3:1.0: USB hub found
hub 3-3:1.0: 4 ports detected
=================================================================
Change-Id: I856402aa128db0c4ba092e1c2a66e29bc9165c40
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64988
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add craaskbowl supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K3LKBKB0BM-MGCP
2. Hynix H9JCNNNCP3MLYR-N6E
BUG=b:235134420
TEST=Use part_id_gen to generate related settings
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I5f6d1b1b988468d0918df20a34a3145af30a65d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64858
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add a mem_parts_used.txt, generate Makefile.inc and
dram_id.generated.txt for this part.
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 0 (0000)
MT62F512M32D2DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 1 (0001)
H9JCNNNCP3MLYR-N6E 0 (0000)
K3LKBKB0BM-MGCP 2 (0010)
K3LKLKL0EM-MGCN 3 (0011)
H58G56AK6BX069 2 (0010)
BUG=b:233830713
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: If9f2b65717a05576fa6b4fb1f53133902ff1a7c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64982
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I607205a0d44c71eb26031ced7a8af303efacd6f2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Replace `LNotEqual(a, b)` with `a != b`.
Change-Id: Iae3343e66906a8123b3d8de2b67948f286e4ad32
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `Multiply (a, b, c)` with `c = a * b`.
Change-Id: I63b8b8a086e2c5ede765855b3c803206edf87690
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `Multiply (a, b, c)` with `c = a * b`.
Change-Id: I19835510b89cd243277f0c9701209c81bdf6ea29
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `Multiply (a, b, c)` with `c = a * b`.
Change-Id: Ib8719143a5a217173b34931e9c0ef02e9895d0a5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `LLess(a, b)` with `a < b`.
Change-Id: Id61c537cc91edbd407fb6429eb4dd2bc8bc7f123
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
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Replace `Multiply (a, b, c)` with `c = a * b`.
Change-Id: Idc24216209bbfe73ef4197d4b8101f0d7e5891f7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
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Replace `LGreaterEqual(a, b)` with `a >= b`.
Change-Id: I5c16893b9c98f36fd2c210ed301c2ebb65f95368
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `LGreaterEqual(a, b)` with `a >= b`.
Change-Id: Id7975a8cad4078a523de2466919982ad540f5dd3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `LNotEqual(a, b)` with `a != b`.
Change-Id: I61ef7b53e851f4c2367cba43ff76b200e9490ad2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `LGreater(a, b)` with `a > b`.
Change-Id: If482b2ad4ba7d4ed1ca8c0695690ede153ed1e2a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
Replace `LGreaterEqual(a, b)` with `a >= b`.
Change-Id: I56e8fdb2503a84ded2bcf183402602579c3f2997
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
|
|
This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C3 | | C0
C2 | | C1
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
BRANCH=firmware-brya-14505.B
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I2153f826d7ff05f42935f08d5d1f5127ac944575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64728
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch uses ACPI _PLD macros to add custom values for USB ports.
C2 C0 A3 A2
+----------------+
| REAR |
| |
| |
| |
| FRONT |
+----------------+
C1 A1 A0
BUG=b:232298007
TEST=emerge-brya coreboot
BRANCH=firmware-brya-14505.B
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I6a9ead24ef9d73bc0b09301cf641009ced0c6810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64732
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
With Cr50, the GPIO EC_IN_RW_ODL is used to determine whether EC is
trusted. However, with Ti50 where corsola has been switched to, it is
determined by Ti50's boot mode. If the boot mode is TRUSTED_RO, the
VB2_CONTEXT_EC_TRUSTED flag will be set in check_boot_mode(). Therefore
in the Ti50 case get_ec_is_trusted() can just return 0.
The current code of get_ec_is_trusted() only checks the GPIO, which
causes the EC to be always considered "trusted". Therefore, correct the
return value to 0 for TPM_GOOGLE_TI50.
BUG=b:235053870
TEST=emerge-corsola coreboot
TEST=firmware-DevMode passed in kingler (with Ti50)
BRANCH=none
Change-Id: I59b16238bfb487832ef618668c0f9addc1ee7937
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64998
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
add fw_config probe for auido and enable BT offload support.
BUG=b:232419816 b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id58e48cc2510d0377040d86bb9dbbb45bec7d624
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
|
Update override devicetree based on schematics.
BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
|
Based on latest schematic to update the gpio table.
BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If30d872af5d729c0ebd468ebfb099192ec682309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
|
Remove EEPROM power source interconnect with camera power on/off
and keep it always on.
There appears to be a rare case where the camera EEPROM is not
able to be read from. As a workaround, this patch leaves the
EEPROM power rail on in S0.
BUG=b:229049914
TEST=tested the changes with redrix 5MP(ov5675/hi556) camera.
Change-Id: I9efab9bb65632a73c1c2635729c38a2aa14c69b2
Signed-off-by: Arec Kao <arec.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The _DSM subfunction for the Nvidia GN20 supports 1 additional
subfunction, known as GPS, which is required to support GPU Boost. This
implementation is minimal, essentially letting the GPU manage its own
temperature.
BUG=b:214581372
TEST=abuild
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I21331bd811a13212f3825bda44be44d1b5ae7c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Now that the power sequencing for the GPU is in a better shape, ensure
that the ACPI code that performs power sequencing matches the C code
that does the same.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I797ee99f22a7a6aaacfe54862595674d4ada06ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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During the GPU power down sequence, each power rail should reach below
at least 10% before the next rail is sequenced down; based on scope
shots for a board, conservative delays between each rail are added;
they will likely be more fine-tuned later on.
BUG=b:233959099
TEST=sequence verified by EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I28ada3a01b86996e9c7802f8bd18b9acda6bb343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Currently, the display does not work in steelix. Steelix uses ps8640
eDP bridge IC, which is different from its reference board kingler.
So we should enable ps8640 for steelix.
BUG=b:232195941
TEST=firmware bootsplash is shown on eDP panel of steelix.
Change-Id: I8c6310794c89fc8aa0e69e114c1f7ebd5479c549
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add OVTI8856 information for craask
BUG=b:232656913
TEST=Build and boot on craask
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ice490f31e9ab8fffff6a7a5d24f769efea91188d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add the support LP5 RAM parts for vell:
DRAM Part Name ID to assign Vendor
H58G56AK6BX069 2 (0010) Hynix
BUG=b:227595062
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: Ibe09285c15b28ceeb6ab0d6c94f90e00584ac07d
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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With a combined bootblock+romstage ENV_ROMSTAGE might no
longer evaluate true.
Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Board id is same so use cpuid to decide to use ADL or RPL VBT.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec
Change-Id: I954c228f82110c3e7c8474e47cabab8220ff19b9
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64672
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Take adlrvp_p as a baseline code and add a new variant of ADL RVP
with Raptor Lake silicon.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I880abe0f300118f461523173cc0d50a2fbc99e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
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+----------------+
C0 | | C1
A0 | MLB DB | A1
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+----------------+
BUG=b:232298307
TEST=None
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ic9c45aebaf02a16b755f4731e1e3b46cd5dec829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
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+----------------+
C0 | | C1
A0 | MLB DB |
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+----------------+
BUG=b:232298017
TEST=None
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Idca3dd468f1b9fde37a1bbf20d65768032c7160b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I0d609f0db475877d0ef1f47ab89c34dccb6e16d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Since many vboot settings are heavily tuned for Chrome OS support,
use these vboot kconfigs for the non Chrome OS use case and tune for EHL
CRB vboot support.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ie1ffd4973fb18bbca5c5b9c888a4dd0e662b1574
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Add two combination:
1. ALC5682I-VS and ALC1019
2. NAU88L25 and MAX98360
BUG=b:227165780, b:228879074
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I36d7b5c4e88825ceaa6922d9e3bed366f55a0d81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Remove TODO's for dummy DXIO descriptors, update comment
to reflect what they are. These devices are needed for the
platform to function properly. Also remove the TODO for
DDI descriptors as they are functioning correctly.
BUG=b:232952508
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I1535c08cac3f0bcb30061aba2aa593eb22109387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The Nvidia GPU kernel driver supports another _DSM subfunction which
is known as NVPCF (Nvidia Platform and Control Framework). The
subfunction informs the kernel driver about Dynamic Boost parameters,
which is done at init time, but can also be changed dynamically.
BUG=b:214581372
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7887bfc2e8e1cae606e12502a9eda3a7954c8d7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Set different power limit values using host command to detect charger
type from ec.
Scenario:
1. With 90W customized adapter, set to baseline.
2. With 170W customized adapter, set to performance.
3. With above 90W barrel jack/type-c adapter, set to performance.
4. With below 90W barrel jack/type-c adapter, set to baseline.
BUG=b:231911918
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9c8a5a7de8249e61468e277ec55348b660253c5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I7c50f770c3a7ab261d6ea41f945e2239ba53fd09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia5b6c5c72a1eafe1118e92e4579decb4f4abc9e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ib2d0c6a23b66e6e61cc8ea09a443e19a4b37c66d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Enable clk 1, LTR & AER for PCIe-to-i225 bridge.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I9593f5d0b70f3d231fd1a8f4758b924645392d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64902
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When device tcss_xhci is disabled, boot hang occurs at FSP-S
TcssInit(): "IomReadyCheck Failed!"
Enabling this device fixes the issue.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ie001bd56b403d511c397737fbc214ed64956910d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64901
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Iea5312055305bc3354755607a7bfafa7980c6d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Follow GPIO_Table_0527.xlsx to update gpio configuration.
- Set GPP_A15 to NC.
- Set GPP_A20 to TCP_DP1_HPD (native function1).
BUG=b:225384873
TEST=Build and boot to Chrome OS.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1c7a211c3bef1f1fe4f94345186c33363a90e11f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Follow thermal table from thermal team.
Chang list:
1. Update TEMP_PCT of Active Policy for TSR1.
BUG=b:230829301
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Nereid
BUG=b:233030505
BRANCH=None
TEST=Build FW and test on Nereid board.
Verified thermal throttling successfully when participant reaches temp
threshold as per Passive Policy.
Also, verified system shutdown when Temperature of participants are
reaching threshold as per Critical policy.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: I195f4b507ee57948751f0119735d8350dfce984b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
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