diff options
| author | John Su <john_su@compal.corp-partner.google.com> | 2022-06-01 17:17:09 +0800 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-06-03 15:27:35 +0000 |
| commit | 1f52edb093aef9b70ce10172bc8c759cdaa1c2ba (patch) | |
| tree | c0564e6696fe14eb0b59fa0c6899b4c7d078c7ff /src/mainboard | |
| parent | f0604afa02a62837734b6cc212d6ff1d6c98ba66 (diff) | |
mb/google/brya/var/mithrax: Update DPTF parameters for Mithrax
Follow thermal table from thermal team.
Chang list:
1. Update TEMP_PCT of Active Policy for TSR1.
BUG=b:230829301
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard')
| -rw-r--r-- | src/mainboard/google/brya/variants/mithrax/overridetree.cb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/google/brya/variants/mithrax/overridetree.cb b/src/mainboard/google/brya/variants/mithrax/overridetree.cb index 06426fa386..2318c2c123 100644 --- a/src/mainboard/google/brya/variants/mithrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/mithrax/overridetree.cb @@ -99,11 +99,11 @@ chip soc/intel/alderlake .target = DPTF_TEMP_SENSOR_1, .thresholds = { TEMP_PCT(48, 76), - TEMP_PCT(45, 65), - TEMP_PCT(42, 53), - TEMP_PCT(39, 45), - TEMP_PCT(36, 39), - TEMP_PCT(33, 34), + TEMP_PCT(40, 66), + TEMP_PCT(38, 53), + TEMP_PCT(36, 43), + TEMP_PCT(34, 39), + TEMP_PCT(32, 33), } } }" |