Age | Commit message (Collapse) | Author |
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read code. SBbus reads to RAM now work. Yah!
- Rename the register constants to something I can look at
more easily.
- Make the logic flow match the flow from V1 assembly
- #if 0 out other SMbus functions that are still broken.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Re-enable the SPD dump routine in this Bitworks/IMS code and make
it work like the Asus/p2b. This avoids having to hack the
sdram/generic_dump_spd.c for a single mem controller.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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- New superIO winbond/w83977tf
- Add single memory controller SBbus debug routine
into a file private to the i440bx
This adds support the start of support for an Asus p2b
mainboard. Current limitations are the same as for the
Bitworks IMS board. Reads from the SMbus don't work.
Moving dump_spd_registers() into its own private copy
solves the problem of having to go hack on the version that
included in src/sdram to only do one memory controller.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2351 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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There is one global change to pci_ids.h. The rest are changes for LX. I
ran abuild and it is ok. Not all artec design changes are included as
some of them would adversely affect other mainboards. Indrek will need
to test.
Signed-off-by: Ron Minnich
Signed-off-by: Indrek Kruusa, indrek.kruusa@artecdesign.ee, artec
design.
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add support for NSC pc87351 SuperIO
add Bitworks/IMS manboard config
This is a very basic framework for the i440bx chipset and the
Bitworks IMS board that uses it. Most things are
structure only.
Known issues:
- SMbus reads to the RAM SPD come back
all zero.
- dump_spd_registers() is commented out since it breaks with
the default setting of generic_dump_spd.c where it wants
2 memory controllers.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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disabled.
cs5536: add new entires for SB control etc.
cs5536.c: chip_enabled function moved to chip_init, so it only gets run
once.
IRQ setup improved
gx2def.h: new defines added
vr.h: new file, with new def's for virtual register control.
mainboard config.lb: new entries added for nb and sb control.
chipsetinit.c: new controls added -- I forget all the details :-)
grphinit.c: new function added
northbridge.c: new IRQ control added. FlashChipSetup added, controlled
by chip info setupflash struct member. Currently, if enabled, this hangs
OLPC in linux PCI scan.
chip.h: new struct members added for unwanted device enable, flash setup
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https://openbios.org/roundup/linuxbios/issue44
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breaking a build is intentional. It will be fixed in a bit.
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manage them. Make pci_level_irq global. Add value settings for OLPC
rev_a board. Comment out no-longer-needed code in olpc mainboard.c
-- it is replaced by the settings in Config.lb, and the support
in cs5536.c
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add support for conditional enable of uarta interrupt.
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done for the gx2 north. tested on OLPC.
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Set linuxbios size to 28k. Drop debug level to 8.
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VSAs now required to be nrv2 compressed
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olpc and rumba can now boot linux out of flash. vsa was resized to 64K.
olpc and rumba now used compressed payload -- thanks stefan!
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goodrich pll code
disable havedmi
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We lost a few things, but this is still worth it.
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Default is 255.
This allows mainboard configs for working across various groups
of boards that differ a device that may not loaded.
If you search for a device that is not loaded and max buses is 255
then there can be up to a 8 second delay to search the entire PCI space.
Board configs that know thier max bus can limit this search space.
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http://snapshots.linuxbios.org/stats/abuild-LinuxBIOSv2-2247.log
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again.
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try to fix 0x10000026
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on a SOM-DB2301 baseboard with a SOM-2354 cpu module.
- Also does a slight tweak to the ram test code to make it more
obvious when it fails.
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add ts5300 flag as comment in flashrom utility Makefile
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- some ts5300 code. Let's push this upstream for now.
- fix a typo in device.c
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vsa on geode GX.
There was some bug in setting up stack, what was that?
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other fixes for gx2 ram init.
support for sharplfg00l04 -- not working yet.
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but it fails
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removed some messages
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still get garbage reading smbus.
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modified dell 1850
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memory is next.
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This is just a skeleton, basically, and will most likely not even
compile yet.
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It's still busted.
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disable agp slot in config.lb
fix error in setting up com1 == should be TTYS0_BAUD
note that the uart8250 struct is a bad design, but so is the
uart8250 code.
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48
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store every HT device unit id base and pass those info to acpi
https://openbios.org/roundup/linuxbios/issue46
Note: This version drops the two scripts a and c and creates the dsdt on
the fly from Config.lb using makerule
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timer (or just failed otherwise due to missing udelay)
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to fail later than before.
dos2unix'ed the xe7501devkit files, that might have caused some problems
before.
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new serengeti_leopard specific code
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1201_ht_bus0_dev0_fidvid_mb.diff part 1
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NOTE: This will break the tree so it can be fixed up later
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