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authorStefan Reinauer <stepan@openbios.org>2006-01-05 00:18:41 +0000
committerStefan Reinauer <stepan@openbios.org>2006-01-05 00:18:41 +0000
commitf1c0fc7ff27832c52e1a3305ecb720ec9b29ce1b (patch)
treef4e8ca1abe6a522f2da464eb00e3b857fc2fd367 /src/mainboard
parent0571a95262be0d58dc28a3f0fba2c69dc543b018 (diff)
latest agami/aruma changes. Compiles but won't boot yet
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2154 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/agami/aruma/Config.lb181
-rw-r--r--src/mainboard/agami/aruma/Options.lb25
-rw-r--r--src/mainboard/agami/aruma/acpi_tables.c437
-rw-r--r--src/mainboard/agami/aruma/cache_as_ram_auto.c258
-rw-r--r--src/mainboard/agami/aruma/chip.h1
-rw-r--r--src/mainboard/agami/aruma/cmos.layout7
-rw-r--r--src/mainboard/agami/aruma/dsdt.c1979
-rw-r--r--src/mainboard/agami/aruma/dx/amd8111.asl172
-rw-r--r--src/mainboard/agami/aruma/dx/amd8111_isa.asl176
-rw-r--r--src/mainboard/agami/aruma/dx/amd8111_pic.asl360
-rw-r--r--src/mainboard/agami/aruma/dx/amd8131.asl119
-rw-r--r--src/mainboard/agami/aruma/dx/amd8131_1.asl119
-rw-r--r--src/mainboard/agami/aruma/dx/amdk8_util.asl315
-rw-r--r--src/mainboard/agami/aruma/dx/dsdt_lb.dsl235
-rw-r--r--src/mainboard/agami/aruma/dx/pci1_hc.asl2
-rw-r--r--src/mainboard/agami/aruma/dx/pci2.asl69
-rw-r--r--src/mainboard/agami/aruma/dx/pci2_hc.asl3
-rw-r--r--src/mainboard/agami/aruma/dx/pci3.asl69
-rw-r--r--src/mainboard/agami/aruma/dx/pci4.asl69
-rw-r--r--src/mainboard/agami/aruma/dx/superio.asl1
-rw-r--r--src/mainboard/agami/aruma/fadt.c110
-rw-r--r--src/mainboard/agami/aruma/get_bus_conf.c163
-rw-r--r--src/mainboard/agami/aruma/mptable.c12
-rw-r--r--src/mainboard/agami/aruma/ssdt_lb_x.dsl77
24 files changed, 2753 insertions, 2206 deletions
diff --git a/src/mainboard/agami/aruma/Config.lb b/src/mainboard/agami/aruma/Config.lb
index e2e1557a1f..333b3b6e27 100644
--- a/src/mainboard/agami/aruma/Config.lb
+++ b/src/mainboard/agami/aruma/Config.lb
@@ -41,43 +41,121 @@ arch i386 end
driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
+
+#needed by irq_tables and mptable and acpi_tables
+object get_bus_conf.o
+
if HAVE_ACPI_TABLES
- object acpi_tables.o
- object fadt.o
- object dsdt.o
+ object acpi_tables.o
+ object fadt.o
+
+ makerule dsdt.c
+ depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
+ action "mv dsdt_lb.hex dsdt.c"
+ end
+ object ./dsdt.o
+
+ makerule ssdt.c
+ depends "$(MAINBOARD)/ssdt_lb_x.dsl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/ssdt_lb_x.dsl"
+ action "perl -pi -e 's/AmlCode/AmlCode_ssdt/g' ssdt_lb_x.hex"
+ action "mv ssdt_lb_x.hex ssdt.c"
+ end
+ object ./ssdt.o
+
+ if ACPI_SSDTX_NUM
+ makerule ssdt2.c
+ depends "$(MAINBOARD)/dx/pci2.asl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl"
+ action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
+ action "mv pci2.hex ssdt2.c"
+ end
+ object ./ssdt2.o
+ makerule ssdt3.c
+ depends "$(MAINBOARD)/dx/pci3.asl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci3.asl"
+ action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
+ action "mv pci3.hex ssdt3.c"
+ end
+ object ./ssdt3.o
+ makerule ssdt4.c
+ depends "$(MAINBOARD)/dx/pci4.asl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci4.asl"
+ action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
+ action "mv pci4.hex ssdt4.c"
+ end
+ object ./ssdt4.o
+
+ end
end
+
+
+
object reset.o
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
+if USE_DCACHE_RAM
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
+ if CONFIG_USE_INIT
+ # compile cache_as_ram.c to auto.o
+ makerule ./cache_as_ram_auto.o
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o cache_as_ram_auto.o"
+ end
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
+ else
+ #compile cache_as_ram.c to auto.inc
+ makerule ./cache_as_ram_auto.inc
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+ action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+ end
+
+ end
+else
+
+ ##
+ ## Romcc output
+ ##
+ makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ end
+
+ makerule ./failover.inc
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+ end
+ makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ end
+ makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+ end
+
+end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
+
mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
+
+mainboardinit cpu/x86/32bit/entry32.inc
+if USE_DCACHE_RAM
+ if CONFIG_USE_INIT
+ ldscript /cpu/x86/32bit/entry32.lds
+ end
+
+ if CONFIG_USE_INIT
+ ldscript /cpu/amd/car/cache_as_ram.lds
+ end
+end
##
## Build our reset vector (This is where linuxBIOS is entered)
@@ -90,8 +168,11 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
+if USE_DCACHE_RAM
+else
+ ### Should this be in the northbridge code?
+ mainboardinit arch/i386/lib/cpu_reset.inc
+end
##
## Include an id string (For safe flashing)
@@ -99,14 +180,25 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
+if USE_DCACHE_RAM
+ ##
+ ## Setup Cache-As-Ram
+ ##
+ mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
+ if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover.lds
+ else
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+ end
end
###
@@ -116,18 +208,37 @@ end
##
## Setup RAM
##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
+if USE_DCACHE_RAM
+
+ if CONFIG_USE_INIT
+ initobject cache_as_ram_auto.o
+ else
+ mainboardinit ./cache_as_ram_auto.inc
+ end
+
+else
+
+ ##
+ ## Setup RAM
+ ##
+ mainboardinit cpu/x86/fpu/enable_fpu.inc
+ mainboardinit cpu/x86/mmx/enable_mmx.inc
+ mainboardinit cpu/x86/sse/enable_sse.inc
+ mainboardinit ./auto.inc
+ mainboardinit cpu/x86/sse/disable_sse.inc
+ mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+end
##
## Include the secondary Configuration files
##
+
dir /pc80
-config chip.h
+
+if CONFIG_CHIP_NAME
+ config chip.h
+end
# config for agami/aruma
chip northbridge/amd/amdk8/root_complex
diff --git a/src/mainboard/agami/aruma/Options.lb b/src/mainboard/agami/aruma/Options.lb
index 967b314428..847bf82a48 100644
--- a/src/mainboard/agami/aruma/Options.lb
+++ b/src/mainboard/agami/aruma/Options.lb
@@ -1,6 +1,7 @@
uses HAVE_MP_TABLE
uses HAVE_PIRQ_TABLE
uses HAVE_ACPI_TABLES
+uses ACPI_SSDTX_NUM
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
@@ -8,6 +9,7 @@ uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
@@ -49,14 +51,19 @@ uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
+uses CONFIG_CHIP_NAME
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
+uses SERIAL_CPU_INIT
+
uses ENABLE_APIC_EXT_ID
uses APIC_ID_OFFSET
uses LIFT_BSP_APIC_ID
-
###
### Build options
###
@@ -96,6 +103,9 @@ default IRQ_SLOT_COUNT=23
default HAVE_MP_TABLE=1
default HAVE_ACPI_TABLES=1
+## extra SSDT num
+default ACPI_SSDTX_NUM=3
+
##
## Build code to export a CMOS option table
##
@@ -113,15 +123,24 @@ default LB_CKS_LOC=123
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_CPUS=8
default CONFIG_MAX_PHYSICAL_CPUS=4
+default CONFIG_LOGICAL_CPUS=1
#default ALLOW_HT_OVERCLOCKING=1
-default ENABLE_APIC_EXT_ID=0
+default ENABLE_APIC_EXT_ID=1
default APIC_ID_OFFSET=0x10
default LIFT_BSP_APIC_ID=0
##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcc000
+default DCACHE_RAM_SIZE=0x4000
+default CONFIG_USE_INIT=1
+
+##
## Build code to setup a generic IOAPIC
##
default CONFIG_IOAPIC=1
diff --git a/src/mainboard/agami/aruma/acpi_tables.c b/src/mainboard/agami/aruma/acpi_tables.c
index 004de3d407..823e5e200a 100644
--- a/src/mainboard/agami/aruma/acpi_tables.c
+++ b/src/mainboard/agami/aruma/acpi_tables.c
@@ -1,7 +1,11 @@
/*
* Agami Aruma ACPI support
+ *
+ * Copyright 2005 Stefan Reinauer
+ * Copyright 2005 AMD
+ *
* written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
+ * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
*/
#include <console/console.h>
@@ -9,127 +13,246 @@
#include <arch/acpi.h>
#include <device/pci.h>
#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(unsigned start, unsigned end)
+{
+
+ unsigned i;
+ print_debug("dump_mem:");
+ for (i = start; i < end; i++) {
+ if ((i & 0xf) == 0) {
+ printk_debug("\n%08x:", i);
+ }
+ printk_debug(" %02x",
+ (unsigned char) *((unsigned char *) i));
+ }
+ print_debug("\n");
+}
+#endif
+
+#define HC_POSSIBLE_NUM 8
extern unsigned char AmlCode[];
+extern unsigned char AmlCode_ssdt[];
+
+#if ACPI_SSDTX_NUM >= 1
+extern unsigned char AmlCode_ssdt2[];
+extern unsigned char AmlCode_ssdt3[];
+extern unsigned char AmlCode_ssdt4[];
+//extern unsigned char AmlCode_ssdt5[];
+//extern unsigned char AmlCode_ssdt6[];
+//extern unsigned char AmlCode_ssdt7[];
+//extern unsigned char AmlCode_ssdt8[];
+#endif
#define IO_APIC_ADDR 0xfec00000UL
-unsigned long acpi_dump_apics(unsigned long current)
+extern unsigned char bus_isa;
+extern unsigned char bus_8111_0;
+extern unsigned char bus_8111_1;
+extern unsigned char bus_8131[7][3]; // another 6 8131
+extern unsigned apicid_8111;
+extern unsigned apicid_8131[7][2];
+
+extern unsigned pci1234[];
+extern unsigned hc_possible_num;
+extern unsigned sblk;
+extern unsigned sbdn;
+extern unsigned hcdn[];
+extern unsigned sbdnx[7]; // for all 8131
+
+
+unsigned long acpi_fill_madt(unsigned long current)
{
- unsigned int gsi_base=0x18, ioapic_nr=2, i;
- device_t dev=0;
-
- /* create all subtables for 4p */
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 16);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 17);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 18);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 19);
-
+ unsigned int gsi_base = 0x18;
+
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
/* Write 8111 IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, 1,
- IO_APIC_ADDR, 0);
-
- /* Write the two onboard 8131 IOAPICs */
- for(i = 0; i < 2; i++) {
- if (dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, dev)){
- ACPI_WRITE_MADT_IOAPIC(dev, ioapic_nr);
- ioapic_nr++;
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_8111, IO_APIC_ADDR, 0);
+
+ /* Write all 8131/8132 IOAPICs */
+ {
+ device_t dev;
+ struct resource *res;
+ dev = dev_find_slot(bus_8131[0][0], PCI_DEVFN(sbdnx[0], 1));
+
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_8131[0][0], res->base, gsi_base);
+ gsi_base += 4;
+
+ }
+ }
+ dev = dev_find_slot(bus_8131[0][0], PCI_DEVFN(sbdnx[0] + 1, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_8131[0][1], res->base, gsi_base);
+ gsi_base += 4;
+ }
}
}
- /* The doughter card may contain either 8131 or 8132 */
+ int i;
+ for (i = 1; i < hc_possible_num; i++)
+ { // 0: is hc sblink
+ device_t dev;
+ int j;
+ struct resource *res;
+
+ if ((pci1234[i] & 1) != 1)
+ continue;
- /* Write the 8132 IOAPICs if they exist */
- for(i = 0; i < 4; i++) {
- if (dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7459, dev)){
- ACPI_WRITE_MADT_IOAPIC(dev, ioapic_nr);
- ioapic_nr++;
+ j = (i - 1) * 2 + 1;
+ dev = dev_find_slot(bus_8131[j][0], PCI_DEVFN(sbdnx[j], 1));
+
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_8131[j][0], res->base, gsi_base);
+ gsi_base += 4;
+
+ }
+ }
+ dev =
+ dev_find_slot(bus_8131[j][0],
+ PCI_DEVFN(sbdnx[j] + 1, 1));
+ if (dev)
+ {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_8131[j][1], res->base, gsi_base);
+ gsi_base += 4;
+ }
}
- }
- /* In the event there were no 8132s look for the 8131s
- * but skip the two onboard 8131
- */
- dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, 0);
- dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, dev);
-
- /* Write all 8131 IOAPICs */
- while((dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7451, dev))) {
- ACPI_WRITE_MADT_IOAPIC(dev, ioapic_nr);
- ioapic_nr++;
+ dev =
+ dev_find_slot(bus_8131[j + 1][0],
+ PCI_DEVFN(sbdnx[j + 1], 1));
+
+ if (dev)
+ {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_8131[j + 1][0], res->base, gsi_base);
+ gsi_base += 4;
+
+ }
+ }
+ dev = dev_find_slot(bus_8131[j + 1][0], PCI_DEVFN(sbdnx[j + 1] + 1, 1));
+ if (dev)
+ {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ apicid_8131[j + 1][1], res->base, gsi_base);
+ gsi_base += 4;
+ }
+ }
+
+
}
-
- current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
- current, 1, 0, 2, 0 );
- current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
- current, 1, 0, 2, 0 );
+
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 5);
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edige-triggered, Active high */
+
+
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapic_nmis(current, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
return current;
}
+//FIXME: next could be moved to northbridge/amd/amdk8/amdk8_acpi.c or cpu/amd/k8/k8_acpi.c begin
+static void int_to_stream(uint32_t val, uint8_t * dest)
+{
+ int i;
+ for (i = 0; i < 4; i++) {
+ *(dest + i) = (val >> (8 * i)) & 0xff;
+ }
+}
+
+extern void get_bus_conf(void);
-/* The next two tables are used by our DSDT and are freely defined
- * here. This construct is used because the bus numbers containing
- * the 8131 bridges may vary so that we need to pass LinuxBIOS
- * knowledge into the DSDT
- */
-typedef struct lnxc_busses {
- u8 secondary;
- u8 subordinate;
-} acpi_lnxb_busses_t;
-
-typedef struct acpi_lnxb {
- struct acpi_table_header header;
- acpi_lnxb_busses_t busses[5];
-} acpi_lnxb_t;
-
-/* special linuxbios acpi table */
-void acpi_create_lnxb(acpi_lnxb_t *lnxb)
+static void update_ssdt(void *ssdt)
{
+ uint8_t *BUSN;
+ uint8_t *MMIO;
+ uint8_t *PCIO;
+ uint8_t *SBLK;
+ uint8_t *TOM1;
+ uint8_t *HCLK;
+ uint8_t *SBDN;
+ uint8_t *HCDN;
+ int i;
device_t dev;
- int busidx=0;
-
- acpi_header_t *header=&(lnxb->header);
+ uint32_t dword;
+ msr_t msr;
- /* fill out header fields */
- memcpy(header->signature, "LNXB", 4);
- memcpy(header->oem_id, OEM_ID, 6);
- memcpy(header->oem_table_id, "LNXBIOS ", 8);
- memcpy(header->asl_compiler_id, ASLC, 4);
+ BUSN = ssdt + 0x3a; //+5 will be next BUSN
+ MMIO = ssdt + 0x57; //+5 will be next MMIO
+ PCIO = ssdt + 0xaf; //+5 will be next PCIO
+ SBLK = ssdt + 0xdc; // one byte
+ TOM1 = ssdt + 0xe3; //
+ HCLK = ssdt + 0xfa; //+5 will be next HCLK
+ SBDN = ssdt + 0xed; //
+ HCDN = ssdt + 0x12a; //+5 will be next HCDN
- header->length = sizeof(acpi_lnxb_t);
- header->revision = 1;
+ dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
- /*
- * Write external 8131 bus ranges
- */
- /* first skip the onboard 8131 */
- dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, 0);
- dev=dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, dev);
-
- /* now look at the last 8131 in each chain,
- * as it contains the valid bus ranges
- */
- while((dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x7450, dev))
- && busidx<5 ) {
- int subu, fn, slot;
- acpi_lnxb_busses_t *busses;
-
- if(PCI_SLOT(dev->path.u.pci.devfn)!=4)
- continue;
-
- busses=&(lnxb->busses[busidx]);
- lnxb->busses[busidx].secondary = dev->bus->secondary;
- lnxb->busses[busidx].subordinate =
- pci_read_config8(dev, PCI_SUBORDINATE_BUS);
-
- busidx++;
+ for (i = 0; i < 4; i++) {
+ dword = pci_read_config32(dev, 0xe0 + i * 4);
+ int_to_stream(dword, BUSN + i * 5);
}
- header->checksum = acpi_checksum((void *)lnxb, sizeof(acpi_lnxb_t));
-}
+ for (i = 0; i < 0x10; i++) {
+ dword = pci_read_config32(dev, 0x80 + i * 4);
+ int_to_stream(dword, MMIO + i * 5);
+ }
+
+ for (i = 0; i < 0x08; i++) {
+ dword = pci_read_config32(dev, 0xc0 + i * 4);
+ int_to_stream(dword, PCIO + i * 5);
+ }
+
+ *SBLK = (uint8_t) (sblk);
+
+ msr = rdmsr(TOP_MEM);
+ int_to_stream(msr.lo, TOM1);
+
+ for (i = 0; i < hc_possible_num; i++) {
+ int_to_stream(pci1234[i], HCLK + i * 5);
+ int_to_stream(hcdn[i], HCDN + i * 5);
+ }
+ for (i = hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+ int_to_stream(0x00000000, HCLK + i * 5);
+ int_to_stream(hcdn[i], HCDN + i * 5);
+ }
+
+ int_to_stream(sbdn, SBDN);
+
+}
+//end
unsigned long write_acpi_tables(unsigned long start)
{
@@ -138,15 +261,21 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_rsdt_t *rsdt;
acpi_hpet_t *hpet;
acpi_madt_t *madt;
+ acpi_srat_t *srat;
acpi_fadt_t *fadt;
acpi_facs_t *facs;
- acpi_lnxb_t *lnxb;
acpi_header_t *dsdt;
+ acpi_header_t *ssdt;
+ acpi_header_t *ssdtx;
+
+ unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM];
+
+ int i;
/* Align ACPI tables to 16byte */
- start = ( start + 0x0f ) & -0x10;
+ start = (start + 0x0f) & -0x10;
current = start;
-
+
printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
/* We need at least an RSDP and an RSDT Table */
@@ -156,60 +285,118 @@ unsigned long write_acpi_tables(unsigned long start)
current += sizeof(acpi_rsdt_t);
/* clear all table memory */
- memset((void *)start, 0, current - start);
-
+ memset((void *) start, 0, current - start);
+
acpi_write_rsdp(rsdp, rsdt);
acpi_write_rsdt(rsdt);
-
+
+ get_bus_conf(); // get sblk, pci1234, and sbdn
+
/*
* We explicitly add these tables later on:
*/
printk_debug("ACPI: * HPET\n");
-
hpet = (acpi_hpet_t *) current;
current += sizeof(acpi_hpet_t);
acpi_create_hpet(hpet);
- acpi_add_table(rsdt,hpet);
+ acpi_add_table(rsdt, hpet);
/* If we want to use HPET Timers Linux wants an MADT */
printk_debug("ACPI: * MADT\n");
-
madt = (acpi_madt_t *) current;
acpi_create_madt(madt);
- current+=madt->header.length;
- acpi_add_table(rsdt,madt);
+ current += madt->header.length;
+ acpi_add_table(rsdt, madt);
- printk_debug("ACPI: * LNXB\n");
- lnxb=(acpi_lnxb_t *)current;
- current += sizeof(acpi_facs_t);
- acpi_create_lnxb(lnxb);
-
+ /* SRAT */
+ printk_debug("ACPI: * SRAT\n");
+ srat = (acpi_srat_t *) current;
+ acpi_create_srat(srat);
+ current += srat->header.length;
+ acpi_add_table(rsdt, srat);
+
+ /* SSDT */
+ printk_debug("ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *) current;
+ current += ((acpi_header_t *) AmlCode_ssdt)->length;
+ memcpy((void *) ssdt, (void *) AmlCode_ssdt,
+ ((acpi_header_t *) AmlCode_ssdt)->length);
+ //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
+ update_ssdt((void *) ssdt);
+ /* recalculate checksum */
+ ssdt->checksum = 0;
+ ssdt->checksum =
+ acpi_checksum((unsigned char *) ssdt, ssdt->length);
+ acpi_add_table(rsdt, ssdt);
+
+#if ACPI_SSDTX_NUM >= 1
+ // we need to make ssdt2 match to PCI2 in pci2.asl,... pci1234[1]
+ AmlCode_ssdtx[1] = AmlCode_ssdt2; // if you have different HT IO card for the same ht slot, here need to check vendor id, to set coresponding SSDT
+ AmlCode_ssdtx[2] = AmlCode_ssdt3;
+ AmlCode_ssdtx[3] = AmlCode_ssdt4;
+// AmlCode_ssdtx[4] = AmlCode_ssdt5;
+// AmlCode_ssdtx[5] = AmlCode_ssdt6;
+// AmlCode_ssdtx[6] = AmlCode_ssdt7;
+// AmlCode_ssdtx[7] = AmlCode_ssdt8;
+
+ //same htio, but different possition? We may have to copy, change HCIN, and recalculate the checknum and add_table
+
+ for (i = 1; i < hc_possible_num; i++) { // 0: is hc sblink
+ if ((pci1234[i] & 1) != 1)
+ continue;
+ printk_debug("ACPI: * SSDT for PCI%d\n", i + 1); //pci0 and pci1 are in dsdt
+ ssdtx = (acpi_header_t *) current;
+ current += ((acpi_header_t *) AmlCode_ssdtx[i])->length;
+ memcpy((void *) ssdtx, (void *) AmlCode_ssdtx[i],
+ ((acpi_header_t *) AmlCode_ssdtx[i])->length);
+ acpi_add_table(rsdt, ssdtx);
+ }
+#endif
+
+
+ /* FACS */
printk_debug("ACPI: * FACS\n");
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
acpi_create_facs(facs);
- dsdt = (acpi_header_t *)current;
- current += ((acpi_header_t *)AmlCode)->length;
- memcpy((void *)dsdt,(void *)AmlCode, \
- ((acpi_header_t *)AmlCode)->length);
+ /* DSDT */
+ printk_debug("ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ current += ((acpi_header_t *) AmlCode)->length;
+ memcpy((void *) dsdt, (void *) AmlCode,
+ ((acpi_header_t *) AmlCode)->length);
+ printk_debug("ACPI: * DSDT @ %08x Length %x\n", dsdt,
+ dsdt->length);
- /* fix up dsdt */
- ((u32 *)dsdt)[11]=((u32)lnxb)+sizeof(acpi_header_t);
-
- /* recalculate checksum */
- dsdt->checksum = 0;
- dsdt->checksum = acpi_checksum(dsdt,dsdt->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
+ /* FDAT */
printk_debug("ACPI: * FADT\n");
-
fadt = (acpi_fadt_t *) current;
current += sizeof(acpi_fadt_t);
- acpi_create_fadt(fadt,facs,dsdt);
- acpi_add_table(rsdt,fadt);
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdt, fadt);
+
+#if DUMP_ACPI_TABLES == 1
+ printk_debug("rsdp\n");
+ dump_mem(rsdp, ((void *) rsdp) + sizeof(acpi_rsdp_t));
+
+ printk_debug("rsdt\n");
+ dump_mem(rsdt, ((void *) rsdt) + sizeof(acpi_rsdt_t));
+
+ printk_debug("madt\n");
+ dump_mem(madt, ((void *) madt) + madt->header.length);
+
+ printk_debug("srat\n");
+ dump_mem(srat, ((void *) srat) + srat->header.length);
+
+ printk_debug("ssdt\n");
+ dump_mem(ssdt, ((void *) ssdt) + ssdt->length);
+
+ printk_debug("fadt\n");
+ dump_mem(fadt, ((void *) fadt) + fadt->header.length);
+#endif
printk_info("ACPI: done.\n");
return current;
}
-
diff --git a/src/mainboard/agami/aruma/cache_as_ram_auto.c b/src/mainboard/agami/aruma/cache_as_ram_auto.c
new file mode 100644
index 0000000000..b820c52aef
--- /dev/null
+++ b/src/mainboard/agami/aruma/cache_as_ram_auto.c
@@ -0,0 +1,258 @@
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 0
+
+#if CONFIG_LOGICAL_CPUS==1
+ #define SET_NB_CFG_54 1
+#endif
+
+//use by raminit
+#define K8_4RANK_DIMM_SUPPORT 1
+
+//used by incoherent_ht
+//#define K8_SCAN_PCI_BUS 1
+//#define K8_ALLOCATE_IO_RANGE 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+
+
+#include <cpu/amd/model_fxx_rev.h>
+
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+#include "lib/memcpy.c"
+#endif
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+static void hard_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+ outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+}
+
+static void memreset_setup(void)
+{
+ if (is_cpu_pre_c0()) {
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ }
+ else {
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ }
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+ if (is_cpu_pre_c0()) {
+ udelay(800);
+ outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ udelay(90);
+ }
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+#define SMBUS_SWITCH1 0x71
+#define SMBUS_SWITCH2 0x73
+ /* Switch 1: pca 9545, Switch 2: pca 9543 */
+ unsigned device = (ctrl->channel0[0]) >> 8;
+ /* Disable all outputs on SMBus switch 1 */
+ smbus_send_byte(SMBUS_SWITCH1, 0x0);
+ /* Select SMBus switch 2 Channel 0/1 */
+ smbus_send_byte(SMBUS_SWITCH2, device);
+
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "sdram/generic_sdram.c"
+
+ /* tyan does not want the default */
+#include "resourcemap.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define CHAN0 0x100
+#define CHAN1 0x200
+
+#include "cpu/amd/car/copy_and_run.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#if USE_FALLBACK_IMAGE == 1
+
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+ unsigned last_boot_normal_x = last_boot_normal();
+
+ /* Is this a cpu only reset? or Is this a secondary cpu? */
+ if ((cpu_init_detectedx) || (!boot_cpu())) {
+ if (last_boot_normal_x) {
+ goto normal_image;
+ } else {
+ goto fallback_image;
+ }
+ }
+
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+
+ enumerate_ht_chain();
+
+ /* Setup the flash access */
+ amd8111_enable_rom();
+
+ /* Is this a deliberate reset by the bios */
+ if (bios_reset_detected() && last_boot_normal_x) {
+ goto normal_image;
+ }
+ /* This is the primary cpu how should I boot? */
+ else if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ normal_image:
+ __asm__ volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+ );
+
+ fallback_image:
+ ;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+#if USE_FALLBACK_IMAGE == 1
+ failover_process(bist, cpu_init_detectedx);
+#endif
+ real_main(bist, cpu_init_detectedx);
+
+}
+
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ static const uint16_t spd_addr [] = {
+ // node 0
+ (0xa0>>1)|CHAN0, (0xa4>>1)|CHAN0, 0, 0,
+ (0xa2>>1)|CHAN0, (0xa6>>1)|CHAN0, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ // node 1
+ (0xa8>>1)|CHAN0, (0xac>>1)|CHAN0, 0, 0,
+ (0xaa>>1)|CHAN0, (0xae>>1)|CHAN0, 0, 0,
+#endif
+#if CONFIG_MAX_PHYSICAL_CPUS > 2
+ // node 2
+ (0xa8>>1)|CHAN1, (0xac>>1)|CHAN1, 0, 0,
+ (0xaa>>1)|CHAN1, (0xae>>1)|CHAN1, 0, 0,
+ // node 3
+ (0xa0>>1)|CHAN1, (0xa4>>1)|CHAN1, 0, 0,
+ (0xa2>>1)|CHAN1, (0xa6>>1)|CHAN1, 0, 0,
+#endif
+ };
+
+ int needs_reset;
+ unsigned cpu_reset = 0;
+ unsigned bsp_apicid = 0;
+ struct mem_controller ctrl[8];
+ unsigned nodes;
+
+ if (bist == 0) {
+ bsp_apicid = init_cpus(cpu_init_detectedx);
+ }
+
+ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ uart_init();
+ console_init();
+
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ setup_aruma_resource_map();
+
+ needs_reset = setup_coherent_ht_domain();
+
+#if CONFIG_LOGICAL_CPUS==1
+ /* here need to make sure last core0 is started, esp for two way system,
+ * (there may be apic id conflicts in that case)
+ */
+ wait_all_core0_started();
+ start_other_cores();
+#endif
+
+ wait_all_aps_started(bsp_apicid);
+
+ needs_reset |= ht_setup_chains_x();
+
+ if (needs_reset) {
+ print_info("ht reset -\r\n");
+ soft_reset();
+ }
+
+ allow_all_aps_stop(bsp_apicid);
+
+ nodes = get_nodes();
+ //It's the time to set ctrl now;
+ fill_mem_ctrl(nodes, ctrl, spd_addr);
+
+ enable_smbus();
+
+ memreset_setup();
+ sdram_initialize(nodes, ctrl);
+
+ post_cache_as_ram(cpu_reset);
+
+}
diff --git a/src/mainboard/agami/aruma/chip.h b/src/mainboard/agami/aruma/chip.h
index ec3254c28b..59ba6712d2 100644
--- a/src/mainboard/agami/aruma/chip.h
+++ b/src/mainboard/agami/aruma/chip.h
@@ -1,5 +1,4 @@
extern struct chip_operations mainboard_agami_aruma_ops;
struct mainboard_agami_aruma_config {
- int nothing;
};
diff --git a/src/mainboard/agami/aruma/cmos.layout b/src/mainboard/agami/aruma/cmos.layout
index c1f3d75316..032703d54a 100644
--- a/src/mainboard/agami/aruma/cmos.layout
+++ b/src/mainboard/agami/aruma/cmos.layout
@@ -67,6 +67,11 @@ enumerations
5 5 4800
5 6 2400
5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
6 6 Notice
6 7 Info
6 8 Debug
@@ -77,7 +82,7 @@ enumerations
7 8 Fallback_Network
7 9 Fallback_HDD
7 10 Fallback_Floppy
-#7 3 ROM
+#7 3 ROM
8 0 200Mhz
8 1 166Mhz
8 2 133Mhz
diff --git a/src/mainboard/agami/aruma/dsdt.c b/src/mainboard/agami/aruma/dsdt.c
deleted file mode 100644
index 753de8a178..0000000000
--- a/src/mainboard/agami/aruma/dsdt.c
+++ /dev/null
@@ -1,1979 +0,0 @@
-/*
- *
- * Intel ACPI Component Architecture
- * ASL Optimizing Compiler / AML Disassembler version 20040220 [May 7 2004]
- * Copyright (C) 2000 - 2004 Intel Corporation
- * Supports ACPI Specification Revision 2.0c
- *
- * Compilation of "latest-dsdt.dsl" - Mon Feb 7 23:20:21 2005
- *
- * C source code output
- *
- */
-unsigned char AmlCode[] =
-{
- 0x44,0x53,0x44,0x54,0x5E,0x3D,0x00,0x00,
- 0x01,0x89,0x4C,0x58,0x42,0x49,0x4F,0x53,
- 0x4C,0x58,0x42,0x49,0x4F,0x53,0x00,0x00,
- 0x17,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C,
- 0x20,0x02,0x04,0x20,0x5B,0x80,0x42,0x49,
- 0x4F,0x53,0x00,0x0C,0x78,0x56,0x34,0x12,
- 0x0A,0xFF,0x5B,0x81,0x38,0x42,0x49,0x4F,
- 0x53,0x01,0x53,0x45,0x42,0x31,0x08,0x53,
- 0x55,0x42,0x31,0x08,0x53,0x45,0x42,0x32,
- 0x08,0x53,0x55,0x42,0x32,0x08,0x53,0x45,
- 0x42,0x33,0x08,0x53,0x55,0x42,0x33,0x08,
- 0x53,0x45,0x42,0x34,0x08,0x53,0x55,0x42,
- 0x34,0x08,0x53,0x45,0x42,0x35,0x08,0x53,
- 0x55,0x42,0x35,0x08,0x08,0x53,0x53,0x31,
- 0x5F,0x01,0x08,0x53,0x53,0x32,0x5F,0x00,
- 0x08,0x53,0x53,0x33,0x5F,0x00,0x08,0x53,
- 0x53,0x34,0x5F,0x01,0x08,0x4D,0x47,0x31,
- 0x42,0x00,0x08,0x4D,0x47,0x31,0x4C,0x00,
- 0x08,0x4D,0x47,0x32,0x42,0x0C,0x00,0x00,
- 0x00,0xAE,0x08,0x4D,0x47,0x32,0x4C,0x0C,
- 0x00,0x00,0x00,0x52,0x08,0x4D,0x47,0x33,
- 0x42,0x0C,0x00,0x00,0x00,0xB1,0x08,0x4D,
- 0x47,0x33,0x4C,0x0C,0x00,0x00,0xC0,0x00,
- 0x08,0x4D,0x47,0x34,0x42,0x0C,0x00,0x00,
- 0xC0,0xB1,0x08,0x4D,0x47,0x34,0x4C,0x0C,
- 0x00,0x00,0x80,0x02,0x08,0x4D,0x47,0x35,
- 0x42,0x0C,0x00,0x00,0x40,0xB4,0x08,0x4D,
- 0x47,0x35,0x4C,0x0C,0x00,0x00,0x80,0x4A,
- 0x08,0x56,0x47,0x41,0x4F,0x00,0x08,0x49,
- 0x4F,0x42,0x30,0x0B,0x00,0xA0,0x08,0x49,
- 0x4F,0x4C,0x30,0x0B,0x00,0x10,0x08,0x49,
- 0x4F,0x42,0x31,0x0B,0x00,0xB0,0x08,0x49,
- 0x4F,0x4C,0x31,0x0B,0x00,0x20,0x08,0x49,
- 0x4F,0x42,0x32,0x00,0x08,0x49,0x4F,0x4C,
- 0x32,0x00,0x08,0x49,0x4F,0x42,0x33,0x00,
- 0x08,0x49,0x4F,0x4C,0x33,0x00,0x08,0x49,
- 0x4F,0x53,0x54,0x0A,0x0B,0x08,0x52,0x4F,
- 0x4D,0x53,0x0C,0x00,0x00,0xF8,0xFF,0x08,
- 0x53,0x50,0x49,0x4F,0x0A,0x2E,0x08,0x49,
- 0x4F,0x31,0x42,0x0B,0x80,0x06,0x08,0x49,
- 0x4F,0x31,0x4C,0x0A,0x80,0x08,0x50,0x4D,
- 0x42,0x53,0x0B,0x00,0x50,0x08,0x50,0x4D,
- 0x4C,0x4E,0x0A,0xC0,0x08,0x47,0x50,0x42,
- 0x53,0x0B,0xC0,0x50,0x08,0x47,0x50,0x4C,
- 0x4E,0x0A,0x20,0x08,0x53,0x4D,0x42,0x53,
- 0x0B,0xE0,0x50,0x08,0x53,0x4D,0x42,0x4C,
- 0x0A,0x20,0x08,0x41,0x50,0x43,0x42,0x0C,
- 0x00,0x00,0xC0,0xFE,0x08,0x41,0x50,0x43,
- 0x4C,0x0B,0x00,0x10,0x14,0x0F,0x52,0x52,
- 0x49,0x4F,0x04,0x70,0x0D,0x52,0x52,0x49,
- 0x4F,0x00,0x5B,0x31,0x14,0x0F,0x52,0x44,
- 0x4D,0x41,0x03,0x70,0x0D,0x72,0x44,0x4D,
- 0x41,0x00,0x5B,0x31,0x08,0x50,0x49,0x43,
- 0x4D,0x00,0x14,0x48,0x04,0x5F,0x50,0x49,
- 0x43,0x01,0xA0,0x09,0x68,0x70,0x0A,0xAA,
- 0x44,0x42,0x47,0x38,0xA1,0x08,0x70,0x0A,
- 0x55,0x44,0x42,0x47,0x38,0x5C,0x2F,0x04,
- 0x5F,0x53,0x42,0x5F,0x50,0x43,0x49,0x41,
- 0x47,0x4F,0x4C,0x41,0x50,0x43,0x4D,0x5F,
- 0x68,0x5C,0x2F,0x04,0x5F,0x53,0x42,0x5F,
- 0x50,0x43,0x49,0x41,0x47,0x4F,0x4C,0x42,
- 0x50,0x43,0x4D,0x5F,0x68,0x70,0x68,0x50,
- 0x49,0x43,0x4D,0x08,0x4F,0x53,0x56,0x52,
- 0xFF,0x14,0x1F,0x4F,0x53,0x46,0x4C,0x00,
- 0xA0,0x0D,0x92,0x93,0x4F,0x53,0x56,0x52,
- 0xFF,0xA4,0x4F,0x53,0x56,0x52,0x70,0x01,
- 0x4F,0x53,0x56,0x52,0xA4,0x4F,0x53,0x56,
- 0x52,0x14,0x4E,0x04,0x4D,0x43,0x54,0x48,
- 0x02,0xA0,0x08,0x95,0x87,0x68,0x87,0x69,
- 0xA4,0x00,0x72,0x87,0x68,0x01,0x60,0x08,
- 0x42,0x55,0x46,0x30,0x11,0x02,0x60,0x08,
- 0x42,0x55,0x46,0x31,0x11,0x02,0x60,0x70,
- 0x68,0x42,0x55,0x46,0x30,0x70,0x69,0x42,
- 0x55,0x46,0x31,0xA2,0x1A,0x60,0x76,0x60,
- 0xA0,0x15,0x92,0x93,0x83,0x88,0x42,0x55,
- 0x46,0x30,0x60,0x00,0x83,0x88,0x42,0x55,
- 0x46,0x31,0x60,0x00,0xA4,0x00,0xA4,0x01,
- 0x14,0x49,0x08,0x47,0x50,0x52,0x57,0x02,
- 0x08,0x50,0x52,0x57,0x50,0x12,0x04,0x02,
- 0x00,0x00,0x70,0x68,0x88,0x50,0x52,0x57,
- 0x50,0x00,0x00,0x70,0x69,0x88,0x50,0x52,
- 0x57,0x50,0x01,0x00,0x70,0x00,0x60,0x7D,
- 0x60,0x79,0x53,0x53,0x31,0x5F,0x01,0x00,
- 0x60,0x7D,0x60,0x79,0x53,0x53,0x32,0x5F,
- 0x0A,0x02,0x00,0x60,0x7D,0x60,0x79,0x53,
- 0x53,0x33,0x5F,0x0A,0x03,0x00,0x60,0x7D,
- 0x60,0x79,0x53,0x53,0x34,0x5F,0x0A,0x04,
- 0x00,0x60,0xA0,0x08,0x7B,0x79,0x01,0x69,
- 0x00,0x60,0x00,0xA1,0x29,0x7A,0x60,0x01,
- 0x60,0xA0,0x18,0x91,0x93,0x4F,0x53,0x46,
- 0x4C,0x01,0x93,0x4F,0x53,0x46,0x4C,0x0A,
- 0x02,0x81,0x60,0x88,0x50,0x52,0x57,0x50,
- 0x01,0x00,0xA1,0x0A,0x82,0x60,0x88,0x50,
- 0x52,0x57,0x50,0x01,0x00,0xA4,0x50,0x52,
- 0x57,0x50,0x08,0x57,0x41,0x4B,0x50,0x12,
- 0x04,0x02,0x00,0x00,0x5B,0x80,0x44,0x45,
- 0x42,0x30,0x01,0x0A,0x80,0x01,0x5B,0x81,
- 0x0B,0x44,0x45,0x42,0x30,0x01,0x44,0x42,
- 0x47,0x38,0x08,0x5B,0x80,0x44,0x45,0x42,
- 0x31,0x01,0x0A,0x90,0x0A,0x02,0x5B,0x81,
- 0x0B,0x44,0x45,0x42,0x31,0x02,0x44,0x42,
- 0x47,0x39,0x10,0x10,0x39,0x5F,0x50,0x52,
- 0x5F,0x5B,0x83,0x0B,0x43,0x50,0x55,0x31,
- 0x01,0x00,0x00,0x00,0x00,0x00,0x5B,0x83,
- 0x0B,0x43,0x50,0x55,0x32,0x02,0x00,0x00,
- 0x00,0x00,0x00,0x5B,0x83,0x0B,0x43,0x50,
- 0x55,0x33,0x03,0x00,0x00,0x00,0x00,0x00,
- 0x5B,0x83,0x0B,0x43,0x50,0x55,0x34,0x04,
- 0x00,0x00,0x00,0x00,0x00,0x10,0x89,0x79,
- 0x02,0x5F,0x53,0x42,0x5F,0x08,0x50,0x52,
- 0x30,0x30,0x12,0x3C,0x04,0x12,0x0D,0x04,
- 0x0C,0xFF,0xFF,0x07,0x00,0x00,0x4C,0x4E,
- 0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,
- 0xFF,0x07,0x00,0x01,0x4C,0x4E,0x4B,0x42,
- 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x07,
- 0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,
- 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x07,0x00,
- 0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00,0x08,
- 0x41,0x52,0x30,0x30,0x12,0x34,0x04,0x12,
- 0x0B,0x04,0x0C,0xFF,0xFF,0x07,0x00,0x00,
- 0x00,0x0A,0x10,0x12,0x0B,0x04,0x0C,0xFF,
- 0xFF,0x07,0x00,0x01,0x00,0x0A,0x11,0x12,
- 0x0C,0x04,0x0C,0xFF,0xFF,0x07,0x00,0x0A,
- 0x02,0x00,0x0A,0x12,0x12,0x0C,0x04,0x0C,
- 0xFF,0xFF,0x07,0x00,0x0A,0x03,0x00,0x0A,
- 0x13,0x08,0x50,0x52,0x30,0x31,0x12,0x2B,
- 0x03,0x12,0x0C,0x04,0x0B,0xFF,0xFF,0x0A,
- 0x03,0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0D,
- 0x04,0x0C,0xFF,0xFF,0x04,0x00,0x00,0x4C,
- 0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,
- 0xFF,0xFF,0x05,0x00,0x00,0x4C,0x4E,0x4B,
- 0x42,0x00,0x08,0x41,0x52,0x30,0x31,0x12,
- 0x25,0x03,0x12,0x0A,0x04,0x0B,0xFF,0xFF,
- 0x0A,0x03,0x00,0x0A,0x13,0x12,0x0B,0x04,
- 0x0C,0xFF,0xFF,0x04,0x00,0x00,0x00,0x0A,
- 0x10,0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x05,
- 0x00,0x00,0x00,0x0A,0x11,0x08,0x50,0x52,
- 0x35,0x32,0x12,0x49,0x05,0x06,0x12,0x0D,
- 0x04,0x0C,0xFF,0xFF,0x01,0x00,0x00,0x4C,
- 0x4E,0x4B,0x42,0x00,0x12,0x0D,0x04,0x0C,
- 0xFF,0xFF,0x01,0x00,0x01,0x4C,0x4E,0x4B,
- 0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,
- 0x01,0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x44,
- 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x41,0x00,
- 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x02,0x00,
- 0x00,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0D,
- 0x04,0x0C,0xFF,0xFF,0x02,0x00,0x01,0x4C,
- 0x4E,0x4B,0x44,0x00,0x08,0x41,0x52,0x35,
- 0x32,0x12,0x4D,0x04,0x06,0x12,0x0B,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x00,0x00,0x0A,
- 0x21,0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x01,0x00,0x0A,0x22,0x12,0x0C,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x0A,0x02,0x00,
- 0x0A,0x23,0x12,0x0C,0x04,0x0C,0xFF,0xFF,
- 0x01,0x00,0x0A,0x03,0x00,0x0A,0x20,0x12,
- 0x0B,0x04,0x0C,0xFF,0xFF,0x02,0x00,0x00,
- 0x00,0x0A,0x22,0x12,0x0B,0x04,0x0C,0xFF,
- 0xFF,0x02,0x00,0x01,0x00,0x0A,0x23,0x08,
- 0x50,0x52,0x35,0x33,0x12,0x49,0x05,0x06,
- 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x01,0x00,
- 0x00,0x4C,0x4E,0x4B,0x42,0x00,0x12,0x0D,
- 0x04,0x0C,0xFF,0xFF,0x01,0x00,0x01,0x4C,
- 0x4E,0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,
- 0xFF,0xFF,0x01,0x00,0x0A,0x02,0x4C,0x4E,
- 0x4B,0x44,0x00,0x12,0x0E,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x0A,0x03,0x4C,0x4E,0x4B,
- 0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,
- 0x02,0x00,0x00,0x4C,0x4E,0x4B,0x43,0x00,
- 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x02,0x00,
- 0x01,0x4C,0x4E,0x4B,0x44,0x00,0x08,0x41,
- 0x52,0x35,0x33,0x12,0x4D,0x04,0x06,0x12,
- 0x0B,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x00,
- 0x00,0x0A,0x25,0x12,0x0B,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x01,0x00,0x0A,0x26,0x12,
- 0x0C,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A,
- 0x02,0x00,0x0A,0x27,0x12,0x0C,0x04,0x0C,
- 0xFF,0xFF,0x01,0x00,0x0A,0x03,0x00,0x0A,
- 0x24,0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x02,
- 0x00,0x00,0x00,0x0A,0x26,0x12,0x0B,0x04,
- 0x0C,0xFF,0xFF,0x02,0x00,0x01,0x00,0x0A,
- 0x27,0x08,0x50,0x52,0x35,0x34,0x12,0x49,
- 0x05,0x06,0x12,0x0D,0x04,0x0C,0xFF,0xFF,
- 0x01,0x00,0x00,0x4C,0x4E,0x4B,0x42,0x00,
- 0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x01,0x00,
- 0x01,0x4C,0x4E,0x4B,0x43,0x00,0x12,0x0E,
- 0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A,0x02,
- 0x4C,0x4E,0x4B,0x44,0x00,0x12,0x0E,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x0A,0x03,0x4C,
- 0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,
- 0xFF,0xFF,0x02,0x00,0x00,0x4C,0x4E,0x4B,
- 0x43,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,
- 0x02,0x00,0x01,0x4C,0x4E,0x4B,0x44,0x00,
- 0x08,0x41,0x52,0x35,0x34,0x12,0x4D,0x04,
- 0x06,0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x00,0x00,0x0A,0x29,0x12,0x0B,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x01,0x00,0x0A,
- 0x2A,0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x0A,0x02,0x00,0x0A,0x2B,0x12,0x0C,
- 0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A,0x03,
- 0x00,0x0A,0x28,0x12,0x0B,0x04,0x0C,0xFF,
- 0xFF,0x02,0x00,0x00,0x00,0x0A,0x2A,0x12,
- 0x0B,0x04,0x0C,0xFF,0xFF,0x02,0x00,0x01,
- 0x00,0x0A,0x2B,0x08,0x50,0x52,0x35,0x35,
- 0x12,0x49,0x05,0x06,0x12,0x0D,0x04,0x0C,
- 0xFF,0xFF,0x01,0x00,0x00,0x4C,0x4E,0x4B,
- 0x42,0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,
- 0x01,0x00,0x01,0x4C,0x4E,0x4B,0x43,0x00,
- 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00,
- 0x0A,0x02,0x4C,0x4E,0x4B,0x44,0x00,0x12,
- 0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A,
- 0x03,0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D,
- 0x04,0x0C,0xFF,0xFF,0x02,0x00,0x00,0x4C,
- 0x4E,0x4B,0x43,0x00,0x12,0x0D,0x04,0x0C,
- 0xFF,0xFF,0x02,0x00,0x01,0x4C,0x4E,0x4B,
- 0x44,0x00,0x08,0x41,0x52,0x35,0x35,0x12,
- 0x4D,0x04,0x06,0x12,0x0B,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x00,0x00,0x0A,0x2D,0x12,
- 0x0B,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x01,
- 0x00,0x0A,0x2E,0x12,0x0C,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x0A,0x02,0x00,0x0A,0x2F,
- 0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x01,0x00,
- 0x0A,0x03,0x00,0x0A,0x2C,0x12,0x0B,0x04,
- 0x0C,0xFF,0xFF,0x02,0x00,0x00,0x00,0x0A,
- 0x2E,0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x02,
- 0x00,0x01,0x00,0x0A,0x2F,0x08,0x50,0x52,
- 0x35,0x36,0x12,0x1E,0x02,0x12,0x0D,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x00,0x4C,0x4E,
- 0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,
- 0xFF,0x02,0x00,0x00,0x4C,0x4E,0x4B,0x42,
- 0x00,0x08,0x41,0x52,0x35,0x36,0x12,0x1A,
- 0x02,0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x00,0x00,0x0A,0x30,0x12,0x0B,0x04,
- 0x0C,0xFF,0xFF,0x02,0x00,0x00,0x00,0x0A,
- 0x31,0x08,0x50,0x52,0x35,0x37,0x12,0x3C,
- 0x04,0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x00,0x4C,0x4E,0x4B,0x41,0x00,0x12,
- 0x0D,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x01,
- 0x4C,0x4E,0x4B,0x42,0x00,0x12,0x0E,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x0A,0x02,0x4C,
- 0x4E,0x4B,0x43,0x00,0x12,0x0E,0x04,0x0C,
- 0xFF,0xFF,0x01,0x00,0x0A,0x03,0x4C,0x4E,
- 0x4B,0x44,0x00,0x08,0x41,0x52,0x35,0x37,
- 0x12,0x34,0x04,0x12,0x0B,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x00,0x00,0x0A,0x34,0x12,
- 0x0B,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x01,
- 0x00,0x0A,0x35,0x12,0x0C,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x0A,0x02,0x00,0x0A,0x36,
- 0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x01,0x00,
- 0x0A,0x03,0x00,0x0A,0x37,0x08,0x50,0x52,
- 0x35,0x38,0x12,0x10,0x01,0x12,0x0D,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x00,0x4C,0x4E,
- 0x4B,0x41,0x00,0x08,0x41,0x52,0x35,0x38,
- 0x12,0x0E,0x01,0x12,0x0B,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x00,0x00,0x0A,0x38,0x08,
- 0x50,0x52,0x35,0x39,0x12,0x3C,0x04,0x12,
- 0x0D,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x00,
- 0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x01,0x4C,0x4E,
- 0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x0A,0x02,0x4C,0x4E,0x4B,
- 0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,
- 0x01,0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,
- 0x00,0x08,0x41,0x52,0x35,0x39,0x12,0x34,
- 0x04,0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x00,0x00,0x0A,0x3C,0x12,0x0B,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x01,0x00,0x0A,
- 0x3D,0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x0A,0x02,0x00,0x0A,0x3E,0x12,0x0C,
- 0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A,0x03,
- 0x00,0x0A,0x3F,0x08,0x50,0x52,0x35,0x41,
- 0x12,0x1E,0x02,0x12,0x0D,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x00,0x4C,0x4E,0x4B,0x41,
- 0x00,0x12,0x0D,0x04,0x0C,0xFF,0xFF,0x02,
- 0x00,0x00,0x4C,0x4E,0x4B,0x42,0x00,0x08,
- 0x41,0x52,0x35,0x41,0x12,0x1A,0x02,0x12,
- 0x0B,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x00,
- 0x00,0x0A,0x40,0x12,0x0B,0x04,0x0C,0xFF,
- 0xFF,0x02,0x00,0x00,0x00,0x0A,0x41,0x08,
- 0x50,0x52,0x35,0x42,0x12,0x3C,0x04,0x12,
- 0x0D,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x00,
- 0x4C,0x4E,0x4B,0x41,0x00,0x12,0x0D,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x01,0x4C,0x4E,
- 0x4B,0x42,0x00,0x12,0x0E,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x0A,0x02,0x4C,0x4E,0x4B,
- 0x43,0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,
- 0x01,0x00,0x0A,0x03,0x4C,0x4E,0x4B,0x44,
- 0x00,0x08,0x41,0x52,0x35,0x42,0x12,0x34,
- 0x04,0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x00,0x00,0x0A,0x44,0x12,0x0B,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x01,0x00,0x0A,
- 0x45,0x12,0x0C,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x0A,0x02,0x00,0x0A,0x46,0x12,0x0C,
- 0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A,0x03,
- 0x00,0x0A,0x47,0x08,0x50,0x52,0x35,0x43,
- 0x12,0x10,0x01,0x12,0x0D,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x00,0x4C,0x4E,0x4B,0x41,
- 0x00,0x08,0x41,0x52,0x35,0x43,0x12,0x0E,
- 0x01,0x12,0x0B,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x00,0x00,0x0A,0x48,0x08,0x50,0x52,
- 0x35,0x44,0x12,0x3C,0x04,0x12,0x0D,0x04,
- 0x0C,0xFF,0xFF,0x01,0x00,0x00,0x4C,0x4E,
- 0x4B,0x41,0x00,0x12,0x0D,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x01,0x4C,0x4E,0x4B,0x42,
- 0x00,0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01,
- 0x00,0x0A,0x02,0x4C,0x4E,0x4B,0x43,0x00,
- 0x12,0x0E,0x04,0x0C,0xFF,0xFF,0x01,0x00,
- 0x0A,0x03,0x4C,0x4E,0x4B,0x44,0x00,0x08,
- 0x41,0x52,0x35,0x44,0x12,0x34,0x04,0x12,
- 0x0B,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x00,
- 0x00,0x0A,0x4C,0x12,0x0B,0x04,0x0C,0xFF,
- 0xFF,0x01,0x00,0x01,0x00,0x0A,0x4D,0x12,
- 0x0C,0x04,0x0C,0xFF,0xFF,0x01,0x00,0x0A,
- 0x02,0x00,0x0A,0x4E,0x12,0x0C,0x04,0x0C,
- 0xFF,0xFF,0x01,0x00,0x0A,0x03,0x00,0x0A,
- 0x4F,0x08,0x50,0x52,0x53,0x41,0x11,0x09,
- 0x0A,0x06,0x23,0xF8,0xDE,0x18,0x79,0x00,
- 0x06,0x50,0x52,0x53,0x41,0x50,0x52,0x53,
- 0x42,0x06,0x50,0x52,0x53,0x41,0x50,0x52,
- 0x53,0x43,0x06,0x50,0x52,0x53,0x41,0x50,
- 0x52,0x53,0x44,0x5B,0x82,0x2B,0x50,0x43,
- 0x49,0x30,0x08,0x5F,0x48,0x49,0x44,0x0C,
- 0x41,0xD0,0x0A,0x03,0x14,0x09,0x5E,0x42,
- 0x4E,0x30,0x30,0x00,0xA4,0x00,0x14,0x0B,
- 0x5F,0x42,0x42,0x4E,0x00,0xA4,0x42,0x4E,
- 0x30,0x30,0x08,0x5F,0x55,0x49,0x44,0x00,
- 0x5B,0x82,0x8F,0xA5,0x01,0x50,0x43,0x49,
- 0x41,0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,
- 0xD0,0x0A,0x03,0x08,0x5F,0x41,0x44,0x52,
- 0x0C,0x01,0x00,0x18,0x00,0x14,0x09,0x5E,
- 0x42,0x4E,0x30,0x31,0x00,0xA4,0x01,0x14,
- 0x0B,0x5F,0x42,0x42,0x4E,0x00,0xA4,0x42,
- 0x4E,0x30,0x31,0x08,0x5F,0x55,0x49,0x44,
- 0x00,0x14,0x16,0x5F,0x50,0x52,0x54,0x00,
- 0xA0,0x0A,0x50,0x49,0x43,0x4D,0xA4,0x41,
- 0x52,0x30,0x30,0xA4,0x50,0x52,0x30,0x30,
- 0x5B,0x82,0x47,0x09,0x50,0x43,0x49,0x31,
- 0x08,0x5F,0x41,0x44,0x52,0x0C,0x00,0x00,
- 0x03,0x00,0x14,0x0F,0x5F,0x50,0x52,0x57,
- 0x00,0xA4,0x47,0x50,0x52,0x57,0x0A,0x08,
- 0x0A,0x04,0x14,0x16,0x5F,0x50,0x52,0x54,
- 0x00,0xA0,0x0A,0x50,0x49,0x43,0x4D,0xA4,
- 0x41,0x52,0x30,0x31,0xA4,0x50,0x52,0x30,
- 0x31,0x5B,0x82,0x2E,0x55,0x53,0x42,0x30,
- 0x08,0x5F,0x41,0x44,0x52,0x00,0x14,0x12,
- 0x5F,0x50,0x53,0x57,0x01,0x7B,0x47,0x4E,
- 0x42,0x4C,0x0B,0xFF,0x7F,0x47,0x4E,0x42,
- 0x4C,0x14,0x0F,0x5F,0x50,0x52,0x57,0x00,
- 0xA4,0x47,0x50,0x52,0x57,0x0A,0x0F,0x0A,
- 0x04,0x5B,0x82,0x2E,0x55,0x53,0x42,0x31,
- 0x08,0x5F,0x41,0x44,0x52,0x01,0x14,0x12,
- 0x5F,0x50,0x53,0x57,0x01,0x7B,0x47,0x4E,
- 0x42,0x4C,0x0B,0xFF,0x7F,0x47,0x4E,0x42,
- 0x4C,0x14,0x0F,0x5F,0x50,0x52,0x57,0x00,
- 0xA4,0x47,0x50,0x52,0x57,0x0A,0x0F,0x0A,
- 0x04,0x5B,0x82,0x42,0xF8,0x53,0x42,0x52,
- 0x47,0x08,0x5F,0x41,0x44,0x52,0x0C,0x00,
- 0x00,0x04,0x00,0x5B,0x82,0x2B,0x50,0x49,
- 0x43,0x5F,0x08,0x5F,0x48,0x49,0x44,0x0B,
- 0x41,0xD0,0x08,0x5F,0x43,0x52,0x53,0x11,
- 0x18,0x0A,0x15,0x47,0x01,0x20,0x00,0x20,
- 0x00,0x00,0x02,0x47,0x01,0xA0,0x00,0xA0,
- 0x00,0x00,0x02,0x22,0x04,0x00,0x79,0x00,
- 0x5B,0x82,0x4E,0x04,0x44,0x4D,0x41,0x44,
- 0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,
- 0x02,0x00,0x08,0x5F,0x43,0x52,0x53,0x11,
- 0x38,0x0A,0x35,0x2A,0x10,0x04,0x47,0x01,
- 0x00,0x00,0x00,0x00,0x00,0x10,0x47,0x01,
- 0x81,0x00,0x81,0x00,0x00,0x03,0x47,0x01,
- 0x87,0x00,0x87,0x00,0x00,0x01,0x47,0x01,
- 0x89,0x00,0x89,0x00,0x00,0x03,0x47,0x01,
- 0x8F,0x00,0x8F,0x00,0x00,0x01,0x47,0x01,
- 0xC0,0x00,0xC0,0x00,0x00,0x20,0x79,0x00,
- 0x5B,0x82,0x47,0x05,0x54,0x4D,0x52,0x5F,
- 0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,0xD0,
- 0x01,0x00,0x08,0x43,0x52,0x53,0x5F,0x11,
- 0x10,0x0A,0x0D,0x47,0x01,0x40,0x00,0x40,
- 0x00,0x00,0x04,0x22,0x01,0x00,0x79,0x00,
- 0x08,0x43,0x52,0x53,0x31,0x11,0x0D,0x0A,
- 0x0A,0x47,0x01,0x40,0x00,0x40,0x00,0x00,
- 0x04,0x79,0x00,0x14,0x1D,0x5F,0x43,0x52,
- 0x53,0x00,0xA0,0x11,0x5E,0x5E,0x2E,0x48,
- 0x50,0x45,0x54,0x5F,0x53,0x54,0x41,0xA4,
- 0x43,0x52,0x53,0x31,0xA4,0x43,0x52,0x53,
- 0x5F,0x5B,0x82,0x47,0x05,0x52,0x54,0x43,
- 0x30,0x08,0x5F,0x48,0x49,0x44,0x0C,0x41,
- 0xD0,0x0B,0x00,0x08,0x43,0x52,0x53,0x5F,
- 0x11,0x10,0x0A,0x0D,0x47,0x01,0x70,0x00,
- 0x70,0x00,0x00,0x02,0x22,0x00,0x01,0x79,
- 0x00,0x08,0x43,0x52,0x53,0x31,0x11,0x0D,
- 0x0A,0x0A,0x47,0x01,0x70,0x00,0x70,0x00,
- 0x00,0x02,0x79,0x00,0x14,0x1D,0x5F,0x43,
- 0x52,0x53,0x00,0xA0,0x11,0x5E,0x5E,0x2E,
- 0x48,0x50,0x45,0x54,0x5F,0x53,0x54,0x41,
- 0xA4,0x43,0x52,0x53,0x31,0xA4,0x43,0x52,
- 0x53,0x5F,0x5B,0x82,0x42,0x05,0x50,0x53,
- 0x32,0x4B,0x08,0x5F,0x48,0x49,0x44,0x0C,
- 0x41,0xD0,0x03,0x03,0x08,0x5F,0x43,0x49,
- 0x44,0x0C,0x41,0xD0,0x03,0x0B,0x14,0x19,
- 0x5F,0x53,0x54,0x41,0x00,0x79,0x01,0x0A,
- 0x0A,0x60,0xA0,0x0B,0x7B,0x49,0x4F,0x53,
- 0x54,0x60,0x00,0xA4,0x0A,0x0F,0xA4,0x00,
- 0x08,0x5F,0x43,0x52,0x53,0x11,0x18,0x0A,
- 0x15,0x47,0x01,0x60,0x00,0x60,0x00,0x00,
- 0x01,0x47,0x01,0x64,0x00,0x64,0x00,0x00,
- 0x01,0x22,0x02,0x00,0x79,0x00,0x14,0x14,
- 0x2E,0x50,0x53,0x32,0x4B,0x5F,0x50,0x52,
- 0x57,0x00,0xA4,0x47,0x50,0x52,0x57,0x0A,
- 0x08,0x0A,0x03,0x5B,0x82,0x41,0x08,0x50,
- 0x53,0x32,0x4D,0x08,0x5F,0x48,0x49,0x44,
- 0x0C,0x41,0xD0,0x0F,0x03,0x08,0x5F,0x43,
- 0x49,0x44,0x0C,0x41,0xD0,0x0F,0x13,0x14,
- 0x19,0x5F,0x53,0x54,0x41,0x00,0x79,0x01,
- 0x0A,0x0C,0x60,0xA0,0x0B,0x7B,0x49,0x4F,
- 0x53,0x54,0x60,0x00,0xA4,0x0A,0x0F,0xA4,
- 0x00,0x08,0x43,0x52,0x53,0x31,0x11,0x08,
- 0x0A,0x05,0x22,0x00,0x10,0x79,0x00,0x08,
- 0x43,0x52,0x53,0x32,0x11,0x18,0x0A,0x15,
- 0x47,0x01,0x60,0x00,0x60,0x00,0x00,0x01,
- 0x47,0x01,0x64,0x00,0x64,0x00,0x00,0x01,
- 0x22,0x00,0x10,0x79,0x00,0x14,0x20,0x5F,
- 0x43,0x52,0x53,0x00,0x79,0x01,0x0A,0x0A,
- 0x60,0xA0,0x0D,0x7B,0x49,0x4F,0x53,0x54,
- 0x60,0x00,0xA4,0x43,0x52,0x53,0x31,0xA1,
- 0x06,0xA4,0x43,0x52,0x53,0x32,0x14,0x14,
- 0x2E,0x50,0x53,0x32,0x4D,0x5F,0x50,0x52,
- 0x57,0x00,0xA4,0x47,0x50,0x52,0x57,0x0A,
- 0x08,0x0A,0x03,0x5B,0x82,0x22,0x53,0x50,
- 0x4B,0x52,0x08,0x5F,0x48,0x49,0x44,0x0C,
- 0x41,0xD0,0x08,0x00,0x08,0x5F,0x43,0x52,
- 0x53,0x11,0x0D,0x0A,0x0A,0x47,0x01,0x61,
- 0x00,0x61,0x00,0x00,0x01,0x79,0x00,0x5B,
- 0x82,0x25,0x43,0x4F,0x50,0x52,0x08,0x5F,
- 0x48,0x49,0x44,0x0C,0x41,0xD0,0x0C,0x04,
- 0x08,0x5F,0x43,0x52,0x53,0x11,0x10,0x0A,
- 0x0D,0x47,0x01,0xF0,0x00,0xF0,0x00,0x00,
- 0x10,0x22,0x00,0x20,0x79,0x00,0x5B,0x82,
- 0x40,0x0B,0x55,0x41,0x52,0x31,0x08,0x5F,
- 0x55,0x49,0x44,0x01,0x08,0x5F,0x48,0x49,
- 0x44,0x0C,0x41,0xD0,0x05,0x01,0x14,0x0C,
- 0x5F,0x53,0x54,0x41,0x00,0xA4,0x44,0x53,
- 0x54,0x41,0x00,0x14,0x0C,0x5F,0x44,0x49,
- 0x53,0x00,0x44,0x43,0x4E,0x54,0x00,0x00,
- 0x14,0x0D,0x5F,0x43,0x52,0x53,0x00,0xA4,
- 0x44,0x43,0x52,0x53,0x00,0x00,0x14,0x0C,
- 0x5F,0x53,0x52,0x53,0x01,0x44,0x53,0x52,
- 0x53,0x68,0x00,0x14,0x0B,0x5F,0x50,0x52,
- 0x53,0x00,0xA4,0x43,0x4D,0x50,0x52,0x08,
- 0x43,0x4D,0x50,0x52,0x11,0x43,0x05,0x0A,
- 0x4F,0x31,0x00,0x47,0x01,0xF8,0x03,0xF8,
- 0x03,0x01,0x08,0x22,0x10,0x00,0x2A,0x00,
- 0x00,0x30,0x47,0x01,0xF8,0x03,0xF8,0x03,
- 0x01,0x08,0x22,0xF8,0x1C,0x2A,0x00,0x00,
- 0x30,0x47,0x01,0xF8,0x02,0xF8,0x02,0x01,
- 0x08,0x22,0xF8,0x1C,0x2A,0x00,0x00,0x30,
- 0x47,0x01,0xE8,0x03,0xE8,0x03,0x01,0x08,
- 0x22,0xF8,0x1C,0x2A,0x00,0x00,0x30,0x47,
- 0x01,0xE8,0x02,0xE8,0x02,0x01,0x08,0x22,
- 0xF8,0x1C,0x2A,0x00,0x00,0x38,0x79,0x00,
- 0x5B,0x82,0x40,0x0F,0x55,0x41,0x52,0x32,
- 0x08,0x5F,0x55,0x49,0x44,0x0A,0x02,0x14,
- 0x0C,0x5F,0x48,0x49,0x44,0x00,0xA4,0x55,
- 0x48,0x49,0x44,0x01,0x14,0x0C,0x5F,0x53,
- 0x54,0x41,0x00,0xA4,0x44,0x53,0x54,0x41,
- 0x01,0x14,0x0C,0x5F,0x44,0x49,0x53,0x00,
- 0x44,0x43,0x4E,0x54,0x01,0x00,0x14,0x0D,
- 0x5F,0x43,0x52,0x53,0x00,0xA4,0x44,0x43,
- 0x52,0x53,0x01,0x01,0x14,0x0C,0x5F,0x53,
- 0x52,0x53,0x01,0x44,0x53,0x52,0x53,0x68,
- 0x01,0x14,0x0B,0x5F,0x50,0x52,0x53,0x00,
- 0xA4,0x43,0x4D,0x50,0x52,0x08,0x43,0x4D,
- 0x50,0x52,0x11,0x4F,0x08,0x0A,0x8B,0x31,
- 0x00,0x47,0x01,0xF8,0x02,0xF8,0x02,0x01,
- 0x08,0x22,0x08,0x00,0x2A,0x00,0x00,0x30,
- 0x47,0x01,0xF8,0x03,0xF8,0x03,0x01,0x08,
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- 0x52,0x53,0x5F,0x11,0x4A,0x07,0x0A,0x76,
- 0x88,0x0D,0x00,0x02,0x0C,0x00,0x00,0x00,
- 0x00,0x00,0xFF,0x00,0x00,0x00,0x00,0x01,
- 0x88,0x0D,0x00,0x01,0x0C,0x03,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x88,0x0D,0x00,0x01,0x0C,0x03,0x00,0x00,
- 0xB0,0x03,0xBB,0x03,0x00,0x00,0x0C,0x00,
- 0x88,0x0D,0x00,0x01,0x0C,0x03,0x00,0x00,
- 0xC0,0x03,0xDF,0x03,0x00,0x00,0x20,0x00,
- 0x87,0x17,0x00,0x00,0x0C,0x03,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x0A,0x00,0xFF,0xFF,
- 0x0B,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x02,0x00,0x87,0x17,0x00,0x00,0x0C,0x03,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x79,0x00,0x8A,0x43,
- 0x52,0x53,0x5F,0x0A,0x64,0x4D,0x49,0x4E,
- 0x35,0x8A,0x43,0x52,0x53,0x5F,0x0A,0x68,
- 0x4D,0x41,0x58,0x35,0x8A,0x43,0x52,0x53,
- 0x5F,0x0A,0x70,0x4C,0x45,0x4E,0x35,0x8A,
- 0x43,0x52,0x53,0x5F,0x0A,0x4A,0x4D,0x49,
- 0x4E,0x34,0x8A,0x43,0x52,0x53,0x5F,0x0A,
- 0x4E,0x4D,0x41,0x58,0x34,0x8A,0x43,0x52,
- 0x53,0x5F,0x0A,0x56,0x4C,0x45,0x4E,0x34,
- 0x8B,0x43,0x52,0x53,0x5F,0x0A,0x18,0x4D,
- 0x49,0x4E,0x49,0x8B,0x43,0x52,0x53,0x5F,
- 0x0A,0x1A,0x4D,0x41,0x58,0x49,0x8B,0x43,
- 0x52,0x53,0x5F,0x0A,0x1E,0x4C,0x45,0x4E,
- 0x49,0x8B,0x43,0x52,0x53,0x5F,0x0A,0x28,
- 0x4D,0x49,0x4E,0x31,0x8B,0x43,0x52,0x53,
- 0x5F,0x0A,0x2A,0x4D,0x41,0x58,0x31,0x8B,
- 0x43,0x52,0x53,0x5F,0x0A,0x2E,0x4C,0x45,
- 0x4E,0x31,0x8B,0x43,0x52,0x53,0x5F,0x0A,
- 0x38,0x4D,0x49,0x4E,0x32,0x8B,0x43,0x52,
- 0x53,0x5F,0x0A,0x3A,0x4D,0x41,0x58,0x32,
- 0x8B,0x43,0x52,0x53,0x5F,0x0A,0x3E,0x4C,
- 0x45,0x4E,0x32,0x8B,0x43,0x52,0x53,0x5F,
- 0x0A,0x08,0x4D,0x49,0x4E,0x42,0x8B,0x43,
- 0x52,0x53,0x5F,0x0A,0x0A,0x4D,0x41,0x58,
- 0x42,0x8B,0x43,0x52,0x53,0x5F,0x0A,0x0E,
- 0x4C,0x45,0x4E,0x42,0x14,0x47,0x0C,0x5F,
- 0x43,0x52,0x53,0x00,0xA0,0x28,0x4D,0x47,
- 0x34,0x4C,0x70,0x4D,0x47,0x34,0x42,0x4D,
- 0x49,0x4E,0x35,0x70,0x4D,0x47,0x34,0x4C,
- 0x4C,0x45,0x4E,0x35,0x70,0x4D,0x47,0x34,
- 0x4C,0x60,0x72,0x4D,0x49,0x4E,0x35,0x76,
- 0x60,0x4D,0x41,0x58,0x35,0xA0,0x3F,0x92,
- 0x93,0x56,0x47,0x41,0x4F,0x0A,0x02,0x70,
- 0x00,0x4D,0x49,0x4E,0x34,0x70,0x00,0x4D,
- 0x41,0x58,0x34,0x70,0x00,0x4C,0x45,0x4E,
- 0x34,0x70,0x00,0x4D,0x49,0x4E,0x31,0x70,
- 0x00,0x4D,0x41,0x58,0x31,0x70,0x00,0x4C,
- 0x45,0x4E,0x31,0x70,0x00,0x4D,0x49,0x4E,
- 0x32,0x70,0x00,0x4D,0x41,0x58,0x32,0x70,
- 0x00,0x4C,0x45,0x4E,0x32,0xA0,0x28,0x49,
- 0x4F,0x4C,0x32,0x70,0x49,0x4F,0x42,0x32,
- 0x4D,0x49,0x4E,0x49,0x70,0x49,0x4F,0x4C,
- 0x32,0x4C,0x45,0x4E,0x49,0x70,0x49,0x4F,
- 0x4C,0x32,0x60,0x72,0x4D,0x49,0x4E,0x49,
- 0x76,0x60,0x4D,0x41,0x58,0x49,0x70,0x53,
- 0x45,0x42,0x32,0x60,0x70,0x60,0x4D,0x49,
- 0x4E,0x42,0x70,0x53,0x55,0x42,0x32,0x60,
- 0x70,0x60,0x4D,0x41,0x58,0x42,0x74,0x53,
- 0x55,0x42,0x32,0x53,0x45,0x42,0x32,0x60,
- 0x72,0x60,0x01,0x4C,0x45,0x4E,0x42,0xA4,
- 0x43,0x52,0x53,0x5F,0x10,0x42,0x23,0x50,
- 0x43,0x49,0x44,0x14,0x0B,0x42,0x4E,0x30,
- 0x44,0x00,0xA4,0x53,0x45,0x42,0x33,0x14,
- 0x11,0x5F,0x53,0x54,0x41,0x00,0xA0,0x08,
- 0x53,0x45,0x42,0x33,0xA4,0x0A,0x0F,0xA4,
- 0x00,0x08,0x43,0x52,0x53,0x5F,0x11,0x4A,
- 0x07,0x0A,0x76,0x88,0x0D,0x00,0x02,0x0C,
- 0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x00,
- 0x00,0x00,0x01,0x88,0x0D,0x00,0x01,0x0C,
- 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x88,0x0D,0x00,0x01,0x0C,
- 0x03,0x00,0x00,0xB0,0x03,0xBB,0x03,0x00,
- 0x00,0x0C,0x00,0x88,0x0D,0x00,0x01,0x0C,
- 0x03,0x00,0x00,0xC0,0x03,0xDF,0x03,0x00,
- 0x00,0x20,0x00,0x87,0x17,0x00,0x00,0x0C,
- 0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x0A,
- 0x00,0xFF,0xFF,0x0B,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x02,0x00,0x87,0x17,0x00,
- 0x00,0x0C,0x03,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x79,
- 0x00,0x8A,0x43,0x52,0x53,0x5F,0x0A,0x64,
- 0x4D,0x49,0x4E,0x35,0x8A,0x43,0x52,0x53,
- 0x5F,0x0A,0x68,0x4D,0x41,0x58,0x35,0x8A,
- 0x43,0x52,0x53,0x5F,0x0A,0x70,0x4C,0x45,
- 0x4E,0x35,0x8A,0x43,0x52,0x53,0x5F,0x0A,
- 0x4A,0x4D,0x49,0x4E,0x34,0x8A,0x43,0x52,
- 0x53,0x5F,0x0A,0x4E,0x4D,0x41,0x58,0x34,
- 0x8A,0x43,0x52,0x53,0x5F,0x0A,0x56,0x4C,
- 0x45,0x4E,0x34,0x8B,0x43,0x52,0x53,0x5F,
- 0x0A,0x18,0x4D,0x49,0x4E,0x49,0x8B,0x43,
- 0x52,0x53,0x5F,0x0A,0x1A,0x4D,0x41,0x58,
- 0x49,0x8B,0x43,0x52,0x53,0x5F,0x0A,0x1E,
- 0x4C,0x45,0x4E,0x49,0x8B,0x43,0x52,0x53,
- 0x5F,0x0A,0x28,0x4D,0x49,0x4E,0x31,0x8B,
- 0x43,0x52,0x53,0x5F,0x0A,0x2A,0x4D,0x41,
- 0x58,0x31,0x8B,0x43,0x52,0x53,0x5F,0x0A,
- 0x2E,0x4C,0x45,0x4E,0x31,0x8B,0x43,0x52,
- 0x53,0x5F,0x0A,0x38,0x4D,0x49,0x4E,0x32,
- 0x8B,0x43,0x52,0x53,0x5F,0x0A,0x3A,0x4D,
- 0x41,0x58,0x32,0x8B,0x43,0x52,0x53,0x5F,
- 0x0A,0x3E,0x4C,0x45,0x4E,0x32,0x8B,0x43,
- 0x52,0x53,0x5F,0x0A,0x08,0x4D,0x49,0x4E,
- 0x42,0x8B,0x43,0x52,0x53,0x5F,0x0A,0x0A,
- 0x4D,0x41,0x58,0x42,0x8B,0x43,0x52,0x53,
- 0x5F,0x0A,0x0E,0x4C,0x45,0x4E,0x42,0x14,
- 0x47,0x0C,0x5F,0x43,0x52,0x53,0x00,0xA0,
- 0x28,0x4D,0x47,0x35,0x4C,0x70,0x4D,0x47,
- 0x35,0x42,0x4D,0x49,0x4E,0x35,0x70,0x4D,
- 0x47,0x35,0x4C,0x4C,0x45,0x4E,0x35,0x70,
- 0x4D,0x47,0x35,0x4C,0x60,0x72,0x4D,0x49,
- 0x4E,0x35,0x76,0x60,0x4D,0x41,0x58,0x35,
- 0xA0,0x3F,0x92,0x93,0x56,0x47,0x41,0x4F,
- 0x0A,0x03,0x70,0x00,0x4D,0x49,0x4E,0x34,
- 0x70,0x00,0x4D,0x41,0x58,0x34,0x70,0x00,
- 0x4C,0x45,0x4E,0x34,0x70,0x00,0x4D,0x49,
- 0x4E,0x31,0x70,0x00,0x4D,0x41,0x58,0x31,
- 0x70,0x00,0x4C,0x45,0x4E,0x31,0x70,0x00,
- 0x4D,0x49,0x4E,0x32,0x70,0x00,0x4D,0x41,
- 0x58,0x32,0x70,0x00,0x4C,0x45,0x4E,0x32,
- 0xA0,0x28,0x49,0x4F,0x4C,0x33,0x70,0x49,
- 0x4F,0x42,0x33,0x4D,0x49,0x4E,0x49,0x70,
- 0x49,0x4F,0x4C,0x33,0x4C,0x45,0x4E,0x49,
- 0x70,0x49,0x4F,0x4C,0x33,0x60,0x72,0x4D,
- 0x49,0x4E,0x49,0x76,0x60,0x4D,0x41,0x58,
- 0x49,0x70,0x53,0x45,0x42,0x33,0x60,0x70,
- 0x60,0x4D,0x49,0x4E,0x42,0x70,0x53,0x55,
- 0x42,0x33,0x60,0x70,0x60,0x4D,0x41,0x58,
- 0x42,0x74,0x53,0x55,0x42,0x33,0x53,0x45,
- 0x42,0x33,0x60,0x72,0x60,0x01,0x4C,0x45,
- 0x4E,0x42,0xA4,0x43,0x52,0x53,0x5F,0x14,
- 0x44,0x05,0x5F,0x50,0x54,0x53,0x01,0x70,
- 0x68,0x44,0x42,0x47,0x38,0x50,0x54,0x53,
- 0x5F,0x68,0x70,0x00,0x88,0x57,0x41,0x4B,
- 0x50,0x00,0x00,0x70,0x00,0x88,0x57,0x41,
- 0x4B,0x50,0x01,0x00,0x70,0x5C,0x2F,0x03,
- 0x5F,0x53,0x42,0x5F,0x50,0x43,0x49,0x41,
- 0x53,0x54,0x4D,0x43,0x5C,0x2F,0x03,0x5F,
- 0x53,0x42,0x5F,0x50,0x43,0x49,0x41,0x53,
- 0x54,0x4D,0x43,0x70,0x01,0x5C,0x2F,0x03,
- 0x5F,0x53,0x42,0x5F,0x50,0x43,0x49,0x41,
- 0x54,0x52,0x50,0x45,0x14,0x36,0x5F,0x57,
- 0x41,0x4B,0x01,0x79,0x68,0x0A,0x04,0x44,
- 0x42,0x47,0x38,0x57,0x41,0x4B,0x5F,0x68,
- 0xA0,0x12,0x83,0x88,0x57,0x41,0x4B,0x50,
- 0x00,0x00,0x70,0x00,0x88,0x57,0x41,0x4B,
- 0x50,0x01,0x00,0xA1,0x0A,0x70,0x68,0x88,
- 0x57,0x41,0x4B,0x50,0x01,0x00,0xA4,0x57,
- 0x41,0x4B,0x50,0x08,0x5F,0x53,0x30,0x5F,
- 0x12,0x06,0x04,0x00,0x00,0x00,0x00,0x08,
- 0x5F,0x53,0x31,0x5F,0x12,0x06,0x04,0x01,
- 0x00,0x00,0x00,0x08,0x5F,0x53,0x34,0x5F,
- 0x12,0x07,0x04,0x0A,0x06,0x00,0x00,0x00,
- 0x08,0x5F,0x53,0x35,0x5F,0x12,0x07,0x04,
- 0x0A,0x07,0x00,0x00,0x00,0x14,0x1D,0x50,
- 0x54,0x53,0x5F,0x01,0xA0,0x16,0x68,0x5C,
- 0x2F,0x04,0x5F,0x53,0x42,0x5F,0x50,0x43,
- 0x49,0x41,0x53,0x42,0x52,0x47,0x53,0x49,
- 0x4F,0x53,0x68,0x14,0x1A,0x57,0x41,0x4B,
- 0x5F,0x01,0x5C,0x2F,0x04,0x5F,0x53,0x42,
- 0x5F,0x50,0x43,0x49,0x41,0x53,0x42,0x52,
- 0x47,0x53,0x49,0x4F,0x57,0x68,
-};
diff --git a/src/mainboard/agami/aruma/dx/amd8111.asl b/src/mainboard/agami/aruma/dx/amd8111.asl
new file mode 100644
index 0000000000..a26d2b4226
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/amd8111.asl
@@ -0,0 +1,172 @@
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111
+ Name (APIC, Package (0x04)
+ {
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
+ })
+
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00}
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
+ // Update the Device Number according to SBDN
+ Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
+
+ Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) {
+ Return (PICM)
+ }
+ Else {
+ Return (APIC)
+ }
+ }
+
+ Device (SBC3)
+ {
+ /* acpi smbus it should be 0x00040003 if 8131 present */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
+ }
+ OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
+ Field (PIRQ, ByteAcc, Lock, Preserve)
+ {
+ PIBA, 8,
+ PIDC, 8
+ }
+/*
+ OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
+ Field (TS3_, DWordAcc, NoLock, Preserve)
+ {
+ PTS3, 16
+ }
+*/
+ }
+
+ Device (HPET)
+ {
+ Name (HPT, 0x00)
+ Name (_HID, EisaId ("PNP0103"))
+ Name (_UID, 0x00)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
+ })
+ Return (BUF0)
+ }
+ }
+
+ Include ("amd8111_pic.asl")
+
+ Include ("amd8111_isa.asl")
+
+ Device (TP2P)
+ {
+ /* 8111 P2P and it should 0x00030000 when 8131 present*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
+ Else { Return (Package (0x02) { 0x08, 0x01 }) }
+ }
+
+ Device (USB0)
+ {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
+ Else { Return (Package (0x02) { 0x0F, 0x01 }) }
+ }
+ }
+
+ Device (USB1)
+ {
+ Name (_ADR, 0x00000001)
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
+ Else { Return (Package (0x02) { 0x0F, 0x01 }) }
+ }
+ }
+
+ Name (APIC, Package (0x0C)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 4
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 3
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
+ })
+
+ Name (PICM, Package (0x0C)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 }, //Slot 4
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 }, //Slot 3
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 }
+ })
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
diff --git a/src/mainboard/agami/aruma/dx/amd8111_isa.asl b/src/mainboard/agami/aruma/dx/amd8111_isa.asl
new file mode 100644
index 0000000000..b68230607e
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/amd8111_isa.asl
@@ -0,0 +1,176 @@
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111 isa
+
+ Device (ISA)
+ {
+ /* lpc 0x00040000 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
+ }
+
+ OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
+ Field (PIRY, ByteAcc, NoLock, Preserve)
+ {
+ Z000, 2, // Parallel Port Range
+ , 1,
+ ECP, 1, // ECP Enable
+ FDC1, 1, // Floppy Drive Controller 1
+ FDC2, 1, // Floppy Drive Controller 2
+ Offset (0x01),
+ Z001, 3, // Serial Port A Range
+ SAEN, 1, // Serial Post A Enabled
+ Z002, 3, // Serial Port B Range
+ SBEN, 1 // Serial Post B Enabled
+ }
+
+ Device (PIC)
+ {
+ Name (_HID, EisaId ("PNP0000"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
+ IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
+ IRQ (Edge, ActiveHigh, Exclusive) {2}
+ })
+ }
+
+ Device (DMA1)
+ {
+ Name (_HID, EisaId ("PNP0200"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
+ IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
+ IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
+ DMA (Compatibility, NotBusMaster, Transfer16) {4}
+ })
+ }
+
+ Device (TMR)
+ {
+ Name (_HID, EisaId ("PNP0100"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
+ IRQ (Edge, ActiveHigh, Exclusive) {0}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
+ IRQ (Edge, ActiveHigh, Exclusive) {8}
+ })
+ }
+
+ Device (SPKR)
+ {
+ Name (_HID, EisaId ("PNP0800"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
+ })
+ }
+
+ Device (COPR)
+ {
+ Name (_HID, EisaId ("PNP0C04"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
+ IRQ (Edge, ActiveHigh, Exclusive) {13}
+ })
+ }
+
+ Device (SYSR)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x00)
+ Name (SYR1, ResourceTemplate ()
+ {
+ IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
+ IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
+ IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
+ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
+ IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
+ IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
+ IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
+ IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
+ IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
+ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
+ IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
+ IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ Return (SYR1)
+ }
+ }
+
+ Device (MEM)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x01)
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
+ Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
+ Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
+ Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
+ Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
+ Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
+ })
+ // Read the Video Memory length
+ CreateDWordField (BUF0, 0x14, CLEN)
+ CreateDWordField (BUF0, 0x10, CBAS)
+
+ ShiftLeft (VGA1, 0x09, Local0)
+ Store (Local0, CLEN)
+
+ Return (BUF0)
+ }
+ }
+
+ Device (PS2M)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IRQNoFlags () {12}
+ })
+ Method (_STA, 0, NotSerialized)
+ {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) { Return (0x0F) }
+ Else { Return (0x00) }
+ }
+ }
+
+ Device (PS2K)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ }
+ Include ("superio.asl")
+
+ }
+
diff --git a/src/mainboard/agami/aruma/dx/amd8111_pic.asl b/src/mainboard/agami/aruma/dx/amd8111_pic.asl
new file mode 100644
index 0000000000..295b6508a1
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/amd8111_pic.asl
@@ -0,0 +1,360 @@
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111 pic LNKA B C D
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x01)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
+ Else { Return (0x0B) } //Enabled
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI1.SBC3.PIBA, 0x0F, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ { // Routing enable
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRA1)
+ Store (Local4, IRA2)
+ }
+
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI1.SBC3.PIBA, 0xF0, \_SB.PCI1.SBC3.PIBA)
+ Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA)
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRB1)
+ CreateByteField (BUFB, 0x02, IRB2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI1.SBC3.PIBA, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRB1)
+ Store (Local4, IRB2)
+ }
+
+ Return (BUFB)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRB1)
+ CreateByteField (Arg0, 0x02, IRB2)
+ ShiftLeft (IRB2, 0x08, Local0)
+ Or (Local0, IRB1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI1.SBC3.PIBA, 0x0F, \_SB.PCI1.SBC3.PIBA)
+ ShiftLeft (Local1, 0x04, Local1)
+ Or (\_SB.PCI1.SBC3.PIBA, Local1, \_SB.PCI1.SBC3.PIBA)
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x03)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI1.SBC3.PIDC, 0x0F, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRA1)
+ Store (Local4, IRA2)
+ }
+
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI1.SBC3.PIDC, 0xF0, \_SB.PCI1.SBC3.PIDC)
+ Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC)
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x04)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRB1)
+ CreateByteField (BUFB, 0x02, IRB2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI1.SBC3.PIDC, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRB1)
+ Store (Local4, IRB2)
+ }
+
+ Return (BUFB)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRB1)
+ CreateByteField (Arg0, 0x02, IRB2)
+ ShiftLeft (IRB2, 0x08, Local0)
+ Or (Local0, IRB1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI1.SBC3.PIDC, 0x0F, \_SB.PCI1.SBC3.PIDC)
+ ShiftLeft (Local1, 0x04, Local1)
+ Or (\_SB.PCI1.SBC3.PIDC, Local1, \_SB.PCI1.SBC3.PIDC)
+ }
+ }
+
+
diff --git a/src/mainboard/agami/aruma/dx/amd8131.asl b/src/mainboard/agami/aruma/dx/amd8131.asl
new file mode 100644
index 0000000000..3761eb063f
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/amd8131.asl
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2005 AMD
+ */
+
+ Device (PG0A)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x14)
+ {
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
+
+ //Cypress Slot A - PIRQ BCDA
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
+
+ //Cypress Slot B - PIRQ CDAB
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
+
+ //Cypress Slot C - PIRQ DABC
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
+
+ //Cypress Slot D - PIRQ ABCD
+ Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
+ Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
+ Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
+ Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
+ })
+ Name (PICM, Package (0x14)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },//Slot 2
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 },
+
+ Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKD, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKA, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKB, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKA, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKB, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKC, 0x00 },
+
+ Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
diff --git a/src/mainboard/agami/aruma/dx/amd8131_1.asl b/src/mainboard/agami/aruma/dx/amd8131_1.asl
new file mode 100644
index 0000000000..1545169e22
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/amd8131_1.asl
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2005 AMD
+ */
+
+ Device (PG1A)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 1), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x14)
+ {
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 2
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
+
+ //Cypress Slot A - PIRQ BCDA
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x19 }, //?
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x18 },
+
+ //Cypress Slot B - PIRQ CDAB
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, //?
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x18 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x19 },
+
+ //Cypress Slot C - PIRQ DABC
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x1B }, //?
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x18 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x19 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x1A },
+
+ //Cypress Slot D - PIRQ ABCD
+ Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x18 }, //?
+ Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x19 },
+ Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x1A },
+ Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x1B }
+ })
+ Name (PICM, Package (0x14)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },//Slot 2
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 },
+
+ Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI1.LNKB, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI1.LNKD, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI1.LNKA, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI1.LNKD, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI1.LNKA, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI1.LNKB, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI1.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI1.LNKA, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI1.LNKB, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI1.LNKC, 0x00 },
+
+ Package (0x04) { 0x0006FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0006FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG1B)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 1), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x1F },// Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x20 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x21 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x22 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI1.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI1.LNKB, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI1.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI1.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
diff --git a/src/mainboard/agami/aruma/dx/amdk8_util.asl b/src/mainboard/agami/aruma/dx/amdk8_util.asl
new file mode 100644
index 0000000000..e9155476c5
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/amdk8_util.asl
@@ -0,0 +1,315 @@
+/*
+ * Copyright 2005 AMD
+ */
+
+//AMD k8 util for BUSB and res range
+
+ Scope (\_SB)
+ {
+
+ Name (OSTB, Ones)
+ Method (OSTP, 0, NotSerialized)
+ {
+ If (LEqual (^OSTB, Ones))
+ {
+ Store (0x00, ^OSTB)
+ }
+
+ Return (^OSTB)
+ }
+
+ Method (SEQL, 2, Serialized)
+ {
+ Store (SizeOf (Arg0), Local0)
+ Store (SizeOf (Arg1), Local1)
+ If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
+
+ Name (BUF0, Buffer (Local0) {})
+ Store (Arg0, BUF0)
+ Name (BUF1, Buffer (Local0) {})
+ Store (Arg1, BUF1)
+ Store (Zero, Local2)
+ While (LLess (Local2, Local0))
+ {
+ Store (DerefOf (Index (BUF0, Local2)), Local3)
+ Store (DerefOf (Index (BUF1, Local2)), Local4)
+ If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
+
+ Increment (Local2)
+ }
+
+ Return (One)
+ }
+
+
+ Method (DADD, 2, NotSerialized)
+ {
+ Store( Arg1, Local0)
+ Store( Arg0, Local1)
+ Add( ShiftLeft(Local1,16), Local0, Local0)
+ Return (Local0)
+ }
+
+
+ Method (GHCE, 1, NotSerialized) // check if the HC enabled
+ {
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
+ Else { Return (0x00) }
+ }
+
+ Method (GHCN, 1, NotSerialized) // get the node num for the HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
+ Return (Local0)
+ }
+
+ Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
+ Return (Local0)
+ }
+
+ Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
+ Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
+ Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
+ Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
+ Return (Local0)
+ }
+
+ Method (GBUS, 2, NotSerialized)
+ {
+ Store (0x00, Local0)
+ While (LLess (Local0, 0x04))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
+ {
+ Return (ShiftRight (And (Local1, 0x00FF0000), 0x10))
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ Return (0x00)
+ }
+
+ Method (GWBN, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0000, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0000,,,)
+ })
+ CreateWordField (BUF0, 0x08, BMIN)
+ CreateWordField (BUF0, 0x0A, BMAX)
+ CreateWordField (BUF0, 0x0E, BLEN)
+ Store (0x00, Local0)
+ While (LLess (Local0, 0x04))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
+ {
+ Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN)
+ Store (ShiftRight (Local1, 0x18), BMAX)
+ Subtract (BMAX, BMIN, BLEN)
+ Increment (BLEN)
+ Return (RTAG (BUF0))
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ Return (RTAG (BUF0))
+ }
+
+ Method (GMEM, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x00000000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000000,,,
+ , AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (BUF0, 0x0A, MMIN)
+ CreateDWordField (BUF0, 0x0E, MMAX)
+ CreateDWordField (BUF0, 0x16, MLEN)
+ Store (0x00, Local0)
+ Store (0x00, Local4)
+ Store (0x00, Local3)
+ While (LLess (Local0, 0x10))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
+ Increment (Local0)
+ Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, And (Local2, 0x07)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
+ {
+ Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
+ Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
+ Or (MMAX, 0xFFFF, MMAX)
+ Subtract (MMAX, MMIN, MLEN)
+
+ If (Local4)
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
+ {
+ Store (\_SB.PCI0.TOM1, MMIN)
+ Subtract (MMAX, MMIN, MLEN)
+ Increment (MLEN)
+ }
+
+ Store (RTAG (BUF0), Local3)
+ }
+
+ Increment (Local4)
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ If (LNot (Local4))
+ {
+ Store (BUF0, Local3)
+ }
+
+ Return (Local3)
+ }
+
+ Method (GIOR, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Address Space Granularity
+ 0x00000000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000000,,,
+ , TypeStatic)
+ })
+ CreateDWordField (BUF0, 0x0A, PMIN)
+ CreateDWordField (BUF0, 0x0E, PMAX)
+ CreateDWordField (BUF0, 0x16, PLEN)
+ Store (0x00, Local0)
+ Store (0x00, Local4)
+ Store (0x00, Local3)
+ While (LLess (Local0, 0x08))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
+ Increment (Local0)
+ Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, And (Local2, 0x07)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
+ {
+ Store (And (Local1, 0x01FFF000), PMIN)
+ Store (And (Local2, 0x01FFF000), PMAX)
+ Or (PMAX, 0x0FFF, PMAX)
+ Subtract (PMAX, PMIN, PLEN)
+ Increment (PLEN)
+
+ If (Local4)
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ If (LGreater (PMAX, PMIN))
+ {
+ If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
+ {
+ Store (0x0D00, PMIN)
+ Subtract (PMAX, PMIN, PLEN)
+ Increment (PLEN)
+ }
+
+ Store (RTAG (BUF0), Local3)
+ Increment (Local4)
+ }
+
+ If (And (Local1, 0x10))
+ {
+ Store (0x03B0, PMIN)
+ Store (0x03DF, PMAX)
+ Store (0x30, PLEN)
+ If (Local4)
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ Store (RTAG (BUF0), Local3)
+ }
+ }
+ }
+
+ Increment (Local4)
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ If (LNot (Local4))
+ {
+ Store (RTAG (BUF0), Local3)
+ }
+
+ Return (Local3)
+ }
+
+ Method (RTAG, 1, NotSerialized)
+ {
+ Store (Arg0, Local0)
+ Store (SizeOf (Local0), Local1)
+ Subtract (Local1, 0x02, Local1)
+ Multiply (Local1, 0x08, Local1)
+ CreateField (Local0, 0x00, Local1, RETB)
+ Store (RETB, Local2)
+ Return (Local2)
+ }
+ }
+
diff --git a/src/mainboard/agami/aruma/dx/dsdt_lb.dsl b/src/mainboard/agami/aruma/dx/dsdt_lb.dsl
new file mode 100644
index 0000000000..dee2cbb674
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/dsdt_lb.dsl
@@ -0,0 +1,235 @@
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_PR)
+ {
+ Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
+ Processor (CPU1, 0x01, 0x00000000, 0x00) {}
+ Processor (CPU2, 0x02, 0x00000000, 0x00) {}
+ Processor (CPU3, 0x03, 0x00000000, 0x00) {}
+
+ }
+
+ Method (FWSO, 0, NotSerialized) { }
+
+ Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
+ Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
+ Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
+ Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ /* BUS0 root bus */
+
+/*
+//hardcode begin
+ Name (BUSN, Package (0x04) { 0x04010003, 0x06050013, 0x00000000, 0x00000000 })
+ Name (MMIO, Package (0x10) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00f43003, 0x00f44f01, 0x0000d003, 0x00efff01, 0x00f40003, 0x00f42f00, 0x00f45003, 0x00f44f00 })
+ Name (PCIO, Package (0x08) { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00001003, 0x00001000, 0x00002003, 0x00002001 })
+ Name (SBLK, 0x00)
+ Name (TOM1, 0x40000000)
+
+ // for AMD opteron we could have four chains, so we will have PCI1, PCI2, PCI3, PCI4
+ // PCI1 must be SBLK Chain
+ // If you have HT IO card that is connected to PCI2, PCI3, PCI4, then you man put Device in SSDT2, SSDT3, SSDT4,
+ // in acpi_tables.c you can link those SSDT to RSDT according to it's presence.
+ // Otherwise put the PCI2, PCI3, PCI4 in this dsdt
+ Name (HCLK, Package (0x04) { 0x00000001, 0x00000011, 0x00000000, 0x00000000 }) //[0,3]=1 enable [4,7]=node_id, [8,15]=linkn
+
+ Name (SBDN, 3) // 8111 UnitID Base
+//hardcode end
+*/
+ External (BUSN)
+ External (MMIO)
+ External (PCIO)
+ External (SBLK)
+ External (TOM1)
+ External (HCLK)
+ External (SBDN)
+ External (HCDN)
+
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00180000)
+ Name (_UID, 0x01)
+ Name (_BBN, 0)
+
+
+ // define L1IC Link1 on node0 init completed, so node1 is installed
+ // We must make sure our bus is 0 ?
+ OperationRegion (LDT1, PCI_Config, 0xA4, 0x01)
+ Field (LDT1, ByteAcc, Lock, Preserve)
+ {
+ , 5,
+ L1IC, 1
+ }
+
+ }
+
+ Device (PCI1)
+ {
+ Name (HCIN, 0x00) // HC1
+ // BUS 1 first HT Chain
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00180000) // Fake
+ Name (_UID, 0x02)
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (0x00, \_SB.PCI0.SBLK))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
+ IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
+ IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x8100, // Address Range Minimum
+ 0xFFFF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x7F00,,,
+ , TypeStatic) //8100h-FFFFh
+
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x000C0000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000000,,,
+ , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
+
+ Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x03AF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x03B0,,,
+ , TypeStatic) //0-CF7h
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x03E0, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0918,,,
+ , TypeStatic) //0-CF7h
+ })
+ \_SB.OSTP ()
+ CreateDWordField (BUF0, 0x3E, VLEN)
+ CreateDWordField (BUF0, 0x36, VMAX)
+ CreateDWordField (BUF0, 0x32, VMIN)
+ ShiftLeft (VGA1, 0x09, Local0)
+ Add (VMIN, Local0, VMAX)
+ Decrement (VMAX)
+ Store (Local0, VLEN)
+ Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+ Return (Local3)
+ }
+
+ Include ("pci1_hc.asl")
+
+ }
+
+ }
+
+ Scope (_GPE)
+ {
+ Method (_L08, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI1, 0x02) //PME# Wakeup
+ }
+
+ Method (_L0F, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI1.TP2P.USB0, 0x02) //USB Wakeup
+ }
+
+ Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
+ {
+ Notify (\_SB.PCI1.PG0B, 0x02)
+ }
+
+ Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
+ {
+ Notify (\_SB.PCI1.PG0A, 0x02)
+ }
+ }
+
+ Method (_PTS, 1, NotSerialized)
+ {
+ Or (Arg0, 0xF0, Local0)
+ Store (Local0, DBG1)
+ }
+/*
+ Method (_WAK, 1, NotSerialized)
+ {
+ Or (Arg0, 0xE0, Local0)
+ Store (Local0, DBG1)
+ }
+*/
+ Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
+ Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
+ {
+ Store (Arg0, PICF)
+ }
+
+ OperationRegion (DEBG, SystemIO, 0x80, 0x01)
+ Field (DEBG, ByteAcc, Lock, Preserve)
+ {
+ DBG1, 8
+ }
+
+ OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
+ Field (EXTM, WordAcc, Lock, Preserve)
+ {
+ AMEM, 32
+ }
+
+ OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
+ Field (VGAM, ByteAcc, Lock, Preserve)
+ {
+ VGA1, 8
+ }
+
+ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+ Field (GRAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x10),
+ FLG0, 8
+ }
+
+ OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
+ Field (GSTS, ByteAcc, NoLock, Preserve)
+ {
+ , 4,
+ IRQR, 1
+ }
+
+ OperationRegion (Z007, SystemIO, 0x21, 0x01)
+ Field (Z007, ByteAcc, NoLock, Preserve)
+ {
+ Z008, 8
+ }
+
+ OperationRegion (Z009, SystemIO, 0xA1, 0x01)
+ Field (Z009, ByteAcc, NoLock, Preserve)
+ {
+ Z00A, 8
+ }
+
+ Include ("amdk8_util.asl")
+
+}
+
diff --git a/src/mainboard/agami/aruma/dx/pci1_hc.asl b/src/mainboard/agami/aruma/dx/pci1_hc.asl
new file mode 100644
index 0000000000..b1e9562f6b
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/pci1_hc.asl
@@ -0,0 +1,2 @@
+ Include ("amd8111.asl") //real SB at first
+ Include ("amd8131.asl")
diff --git a/src/mainboard/agami/aruma/dx/pci2.asl b/src/mainboard/agami/aruma/dx/pci2.asl
new file mode 100644
index 0000000000..7adb5a5e93
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/pci2.asl
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI1.LNKA, DeviceObj)
+ External (\_SB.PCI1.LNKB, DeviceObj)
+ External (\_SB.PCI1.LNKC, DeviceObj)
+ External (\_SB.PCI1.LNKD, DeviceObj)
+
+
+ Device (PCI2)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0x01) // HC2
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00180000))
+ }
+
+ Name (_UID, 0x03)
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ Include ("pci2_hc.asl")
+ }
+ }
+
+}
+
diff --git a/src/mainboard/agami/aruma/dx/pci2_hc.asl b/src/mainboard/agami/aruma/dx/pci2_hc.asl
new file mode 100644
index 0000000000..3f652e7f84
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/pci2_hc.asl
@@ -0,0 +1,3 @@
+ Include ("amd8131.asl")
+
+ Include ("amd8131_1.asl")
diff --git a/src/mainboard/agami/aruma/dx/pci3.asl b/src/mainboard/agami/aruma/dx/pci3.asl
new file mode 100644
index 0000000000..4b62a8ac31
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/pci3.asl
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI1.LNKA, DeviceObj)
+ External (\_SB.PCI1.LNKB, DeviceObj)
+ External (\_SB.PCI1.LNKC, DeviceObj)
+ External (\_SB.PCI1.LNKD, DeviceObj)
+
+
+ Device (PCI3)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0x02) // HC3
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00180000))
+ }
+
+ Name (_UID, 0x04)
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ Include ("pci2_hc.asl")
+ }
+ }
+
+}
+
diff --git a/src/mainboard/agami/aruma/dx/pci4.asl b/src/mainboard/agami/aruma/dx/pci4.asl
new file mode 100644
index 0000000000..ae0700405a
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/pci4.asl
@@ -0,0 +1,69 @@
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI1.LNKA, DeviceObj)
+ External (\_SB.PCI1.LNKB, DeviceObj)
+ External (\_SB.PCI1.LNKC, DeviceObj)
+ External (\_SB.PCI1.LNKD, DeviceObj)
+
+
+ Device (PCI4)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0x03) // HC4
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00180000))
+ }
+
+ Name (_UID, 0x05)
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ Include ("pci2_hc.asl")
+ }
+ }
+
+}
+
diff --git a/src/mainboard/agami/aruma/dx/superio.asl b/src/mainboard/agami/aruma/dx/superio.asl
new file mode 100644
index 0000000000..86a10a94ae
--- /dev/null
+++ b/src/mainboard/agami/aruma/dx/superio.asl
@@ -0,0 +1 @@
+// Include ("w83627hf.asl")
diff --git a/src/mainboard/agami/aruma/fadt.c b/src/mainboard/agami/aruma/fadt.c
index 934195690c..9df0197ccf 100644
--- a/src/mainboard/agami/aruma/fadt.c
+++ b/src/mainboard/agami/aruma/fadt.c
@@ -4,64 +4,71 @@
*/
#include <string.h>
+#include <console/console.h>
#include <arch/acpi.h>
-void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
- acpi_header_t *header=&(fadt->header);
+extern unsigned pm_base; /* pm_base should be set in sb acpi */
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+
+ acpi_header_t *header = &(fadt->header);
+
+ printk_debug("pm_base: 0x%04x\n", pm_base);
/* Prepare the header */
- memset((void *)fadt,0,sizeof(acpi_fadt_t));
- memcpy(header->signature,"FACP",4);
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
header->length = 244;
header->revision = 1;
- memcpy(header->oem_id,OEM_ID,6);
- memcpy(header->oem_table_id,"LXBACPI ",8);
- memcpy(header->asl_compiler_id,ASLC,4);
- header->asl_compiler_revision=0;
-
- fadt->firmware_ctrl=(unsigned long)facs;
- fadt->dsdt= dsdt;
- fadt->res1=0x0;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "LXBACPI ", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 0;
+
+ fadt->firmware_ctrl = (u32) facs;
+ fadt->dsdt = (u32) dsdt;
+ fadt->res1 = 0x0;
// 3=Workstation,4=Enterprise Server, 7=Performance Server
- fadt->preferred_pm_profile=0x03;
- fadt->sci_int=9;
+ fadt->preferred_pm_profile = 0x03;
+ fadt->sci_int = 9;
// disable system management mode by setting to 0:
- fadt->smi_cmd = 0x502f;
- fadt->acpi_enable = 0xe1;
- fadt->acpi_disable = 0x1e;
+ fadt->smi_cmd = 0; //pm_base+0x2f;
+ fadt->acpi_enable = 0xf0;
+ fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
fadt->pstate_cnt = 0xe2;
- fadt->pm1a_evt_blk = 0x5000;
+ fadt->pm1a_evt_blk = pm_base;
fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = 0x5004;
+ fadt->pm1a_cnt_blk = pm_base + 0x04;
fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = 0x0000;
- fadt->pm_tmr_blk = 0x5008;
- fadt->gpe0_blk = 0x5020;
- fadt->gpe1_blk = 0x50b0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 0;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 4;
- fadt->gpe1_blk_len = 8;
- fadt->gpe1_base = 16;
-
- fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101;
+ fadt->pm2_cnt_blk = 0x0000;
+ fadt->pm_tmr_blk = pm_base + 0x08;
+ fadt->gpe0_blk = pm_base + 0x20;
+ fadt->gpe1_blk = pm_base + 0xb0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 0;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 4;
+ fadt->gpe1_blk_len = 8;
+ fadt->gpe1_base = 16;
+
+ fadt->cst_cnt = 0xe3;
+ fadt->p_lvl2_lat = 101;
fadt->p_lvl3_lat = 1001;
- fadt->flush_size = 1024;
- fadt->flush_stride = 16;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
- fadt->day_alrm = 0; // 0x7d these have to be
- fadt->mon_alrm = 0; // 0x7e added to cmos.layout
- fadt->century = 0; // 0x7f to make rtc alrm work
- fadt->iapc_boot_arch = 0x3; // See table 5-11
- fadt->flags = 0xa5;
-
+ fadt->day_alrm = 0; // 0x7d these have to be
+ fadt->mon_alrm = 0; // 0x7e added to cmos.layout
+ fadt->century = 0; // 0x7f to make rtc alrm work
+ fadt->iapc_boot_arch = 0x3; // See table 5-11
+ fadt->flags = 0x25;
+
fadt->res2 = 0;
fadt->reset_reg.space_id = 1;
@@ -71,17 +78,17 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->reset_reg.addrl = 0xcf9;
fadt->reset_reg.addrh = 0x0;
- fadt->reset_value = 0x06;
- fadt->x_firmware_ctl_l = facs;
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (u32) facs;
fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = dsdt;
+ fadt->x_dsdt_l = (u32) dsdt;
fadt->x_dsdt_h = 0;
fadt->x_pm1a_evt_blk.space_id = 1;
fadt->x_pm1a_evt_blk.bit_width = 32;
fadt->x_pm1a_evt_blk.bit_offset = 0;
fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = 0x5000;
+ fadt->x_pm1a_evt_blk.addrl = pm_base;
fadt->x_pm1a_evt_blk.addrh = 0x0;
fadt->x_pm1b_evt_blk.space_id = 1;
@@ -96,7 +103,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_pm1a_cnt_blk.bit_width = 16;
fadt->x_pm1a_cnt_blk.bit_offset = 0;
fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = 0x5004;
+ fadt->x_pm1a_cnt_blk.addrl = pm_base + 4;
fadt->x_pm1a_cnt_blk.addrh = 0x0;
fadt->x_pm1b_cnt_blk.space_id = 1;
@@ -119,7 +126,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = 0x5008;
+ fadt->x_pm_tmr_blk.addrl = pm_base + 0x08;
fadt->x_pm_tmr_blk.addrh = 0x0;
@@ -127,7 +134,7 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = 0x5020;
+ fadt->x_gpe0_blk.addrl = pm_base + 0x20;
fadt->x_gpe0_blk.addrh = 0x0;
@@ -135,9 +142,10 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_gpe1_blk.bit_width = 64;
fadt->x_gpe1_blk.bit_offset = 16;
fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = 0x50b0;
+ fadt->x_gpe1_blk.addrl = pm_base + 0xb0;
fadt->x_gpe1_blk.addrh = 0x0;
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+ header->checksum =
+ acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
}
diff --git a/src/mainboard/agami/aruma/get_bus_conf.c b/src/mainboard/agami/aruma/get_bus_conf.c
new file mode 100644
index 0000000000..3a08b7ac8d
--- /dev/null
+++ b/src/mainboard/agami/aruma/get_bus_conf.c
@@ -0,0 +1,163 @@
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+//busnum is default
+unsigned char bus_isa = 7;
+unsigned char bus_8111_0 = 1;
+unsigned char bus_8111_1 = 4;
+unsigned char bus_8131[7][3]; // another 6 8131
+unsigned apicid_8111;
+unsigned apicid_8131[7][2];
+
+unsigned sblk;
+unsigned pci1234[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ 0x0000ff0,
+ 0x0000f10,
+ 0x0000f20,
+ 0x0000f30,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0
+};
+unsigned hc_possible_num;
+unsigned sbdn;
+unsigned hcdn[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+ 0x20202020,
+ 0x20202020,
+ 0x20202020,
+ 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+};
+
+unsigned sbdnx[7]; // for all 8131
+
+extern void get_sblk_pci1234(void);
+
+static unsigned get_bus_conf_done = 0;
+
+void get_bus_conf(void)
+{
+
+ unsigned apicid_base;
+
+ device_t dev;
+
+ int i;
+
+ if (get_bus_conf_done == 1)
+ return; //do it only once
+
+ get_bus_conf_done = 1;
+
+ hc_possible_num = sizeof(pci1234) / sizeof(pci1234[0]);
+
+ get_sblk_pci1234();
+
+
+ sbdn = ((hcdn[0] >> 8) & 0xff); // first byte of first chain
+ sbdnx[0] = (hcdn[0] & 0xff);
+
+ for (i = 0; i < hc_possible_num; i++) {
+ sbdnx[i * 2 + 1] = hcdn[i] & 0xff;
+ sbdnx[i * 2 + 2] = (hcdn[i] >> 8) & 0xff;
+ }
+
+ bus_8131[0][0] = (pci1234[0] >> 16) & 0xff;
+ bus_8111_0 = bus_8131[0][0];
+
+ /* 8111 */
+ dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sbdn, 0));
+ if (dev) {
+ bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+// printk_debug("bus_isa=%d\n",bus_isa);
+ } else {
+ printk_debug
+ ("ERROR - could not find PCI %02x:03.0, using defaults\n",
+ bus_8111_0);
+ }
+
+
+ /* 8131-1 */
+ bus_8131[0][0] = 1;
+ dev = dev_find_slot(bus_8131[0][0], PCI_DEVFN(sbdnx[1], 0));
+ if (dev) {
+ bus_8131[0][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ } else {
+ printk_debug
+ ("ERROR - could not find PCI %02x:01.0, using defaults\n",
+ bus_8131[0][0]);
+ }
+
+
+ /* 8132-2 */
+ dev = dev_find_slot(bus_8131[0][0], PCI_DEVFN(sbdnx[1] + 1, 0));
+ if (dev) {
+ bus_8131[0][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ } else {
+ printk_debug
+ ("ERROR - could not find PCI %02x:02.0, using defaults\n",
+ bus_8131[0][0]);
+ }
+
+ apicid_base = get_apicid_base(15);
+
+ apicid_8111 = apicid_base++;
+
+ apicid_8131[0][0] = apicid_base++;
+
+ apicid_8131[0][1] = apicid_base++;
+
+
+ /* HT chain 1 */
+ for (i = 1; i < 4; i++) {
+ if (pci1234[i] & 0x1) {
+ int j = (i - 1) * 2 + 1;
+ bus_8131[j][0] = (pci1234[i] >> 16) & 0xff;
+ /* 8131 */
+ dev = dev_find_slot(bus_8131[j][0], PCI_DEVFN(sbdnx[j], 0));
+ if (dev) {
+ bus_8131[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ apicid_8131[j][0] = apicid_base++;
+ dev = dev_find_slot(bus_8131[j][0], PCI_DEVFN(sbdnx[j] + 1, 0));
+ if (dev) {
+ bus_8131[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ apicid_8131[j][1] = apicid_base++;
+
+ bus_8131[j + 1][0] = bus_8131[j][0];
+ /* 8131 */
+ dev = dev_find_slot(bus_8131[j + 1][0], PCI_DEVFN(sbdnx[j + 1], 0));
+ if (dev) {
+ bus_8131[j + 1][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ apicid_8131[j + 1][0] = apicid_base++;
+
+ dev = dev_find_slot(bus_8131[i + 1][0], PCI_DEVFN(sbdnx[j + 1] + 1, 0));
+ if (dev) {
+ bus_8131[j + 1][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+
+ }
+ apicid_8131[j + 1][0] = apicid_base++;
+ }
+ }
+}
diff --git a/src/mainboard/agami/aruma/mptable.c b/src/mainboard/agami/aruma/mptable.c
index b598a79524..37776cfa03 100644
--- a/src/mainboard/agami/aruma/mptable.c
+++ b/src/mainboard/agami/aruma/mptable.c
@@ -16,17 +16,7 @@ do { \
smp_write_ioapic(mc, id, version, res->base); \
} while(0);
-unsigned get_apicid_base(unsigned ioapic_num)
-{
- device_t dev;
- unsigned apicid_base;
-
- dev = dev_find_slot(0, PCI_DEVFN(0x18,0));
- apicid_base = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1;
-
- return apicid_base;
-}
-
+unsigned get_apicid_base(unsigned ioapic_num);
void *smp_write_config_table(void *v)
{
diff --git a/src/mainboard/agami/aruma/ssdt_lb_x.dsl b/src/mainboard/agami/aruma/ssdt_lb_x.dsl
new file mode 100644
index 0000000000..7e835b6632
--- /dev/null
+++ b/src/mainboard/agami/aruma/ssdt_lb_x.dsl
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT.aml", "SSDT", 1, "AMD-K8", "AMD-ACPI", 100925440)
+{
+ /*
+ * These objects were referenced but not defined in this table
+ */
+ External (\_SB_.PCI0, DeviceObj)
+
+ Scope (\_SB.PCI0)
+ {
+ Name (BUSN, Package (0x04)
+ {
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444
+ })
+ Name (MMIO, Package (0x10)
+ {
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee,
+ 0x11111111,
+ 0x22222222
+ })
+ Name (PCIO, Package (0x08)
+ {
+ 0x77777777,
+ 0x88888888,
+ 0x99999999,
+ 0xaaaaaaaa,
+ 0xbbbbbbbb,
+ 0xcccccccc,
+ 0xdddddddd,
+ 0xeeeeeeee
+ })
+ Name (SBLK, 0x11)
+ Name (TOM1, 0xaaaaaaaa)
+ Name (SBDN, 0xbbbbbbbb)
+ Name (HCLK, Package (0x08)
+ {
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888
+ })
+ Name (HCDN, Package (0x08)
+ {
+ 0x11111111,
+ 0x22222222,
+ 0x33333333,
+ 0x44444444,
+ 0x55555555,
+ 0x66666666,
+ 0x77777777,
+ 0x88888888
+ })
+ }
+}
+
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 12:01:18 +0000