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authorLi-Ta Lo <ollie@lanl.gov>2006-03-13 21:58:43 +0000
committerLi-Ta Lo <ollie@lanl.gov>2006-03-13 21:58:43 +0000
commit71eae20b305fc894f2d6e35bd5d58084153ea8b6 (patch)
tree54096e3c09ca22adee49c18b095b23dad2a2dc50 /src/mainboard
parentec9cdc980fe3f6c5037b76907550e1323958da75 (diff)
failed attempt to do early init for cs5535. Almost there but
still get garbage reading smbus. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2192 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard')
-rw-r--r--src/mainboard/amd/rumba/auto.c71
1 files changed, 10 insertions, 61 deletions
diff --git a/src/mainboard/amd/rumba/auto.c b/src/mainboard/amd/rumba/auto.c
index 9163374cff..6b3586b205 100644
--- a/src/mainboard/amd/rumba/auto.c
+++ b/src/mainboard/amd/rumba/auto.c
@@ -9,48 +9,32 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
-#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/bist.h"
#include "cpu/x86/msr.h"
+#include <cpu/amd/gx2def.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void dump_msr(void)
-{
- int i = 0;
- msr_t msr;
-
- static const unsigned int msrs[] = { 0x20000018, 0x20000019, 0x0};
-
- while (msrs[i] != 0) {
- msr = rdmsr(msrs[i]);
- print_debug("MSR ");
- print_debug_hex32(msrs[i]);
- print_debug("=> ");
- print_debug_hex32(msr.hi);
- print_debug(":");
- print_debug_hex32(msr.lo);
- print_debug("\n\r");
- i++;
- }
-}
-//#include "lib/delay.c"
+#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
+#include "southbridge/amd/cs5535/cs5535_early_setup.c"
#include "northbridge/amd/gx2/raminit.h"
#include "northbridge/amd/gx2/raminit.c"
#include "sdram/generic_sdram.c"
+#include "northbridge/amd/gx2/pll_reset.c"
static void msr_init(void)
{
-
__builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
+
__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
__builtin_wrmsr(0x10000026, 0x400fffc0, 0x2cfbc040);
__builtin_wrmsr(0x10000027, 0xfff00000, 0xff);
__builtin_wrmsr(0x10000028, 0x7bf00100, 0x2000000f);
__builtin_wrmsr(0x1000002c, 0xff030003, 0x20000000);
+
__builtin_wrmsr(0x10000080, 0x3, 0x0);
__builtin_wrmsr(0x40000020, 0xfff80, 0x20000000);
@@ -60,47 +44,12 @@ static void msr_init(void)
__builtin_wrmsr(0x40000029, 0x7bf00100, 0x2000000f);
__builtin_wrmsr(0x4000002d, 0xff030003, 0x20000000);
- __builtin_wrmsr(0x400000e3, 0xf0309c10, 0x0);
- __builtin_wrmsr(0xc0002001, 0x86002, 0x0);
- __builtin_wrmsr(0x80002001, 0x86002, 0x0);
- __builtin_wrmsr(0xa0002001, 0x86002, 0x0);
__builtin_wrmsr(0x50002001, 0x27, 0x0);
__builtin_wrmsr(0x4c002001, 0x1, 0x0);
}
-static void pll_reset(void)
-{
- msr_t msr;
-
- msr = rdmsr(0x4c000014);
- print_debug("CGLP_SYS_RSTPLL ");
- print_debug_hex32(msr.hi);
- print_debug(":");
- print_debug_hex32(msr.lo);
- print_debug("\n\r");
-
- if ((msr.lo >> 26) & 0x3F) {
- print_debug("reboot from BIOS reset\n\r");
- return;
- }
- print_debug("prgramming PLL\n\r");
-
- msr.hi = 0x00000019;
- msr.lo = 0x06de0378;
- wrmsr(0x4c000014, msr);
- msr.lo |= ((0xde << 16) | (1 << 26) | (1 << 24));
- wrmsr(0x4c000014, msr);
-
- print_debug("Reset PLL\n\r");
- msr.lo |= ((1<<14) |(1<<13) | (1<<0));
- wrmsr(0x4c000014,msr);
-
- print_debug("should not be here\n\r");
-
-
-}
static void main(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
@@ -108,15 +57,15 @@ static void main(unsigned long bist)
};
msr_init();
-
+
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
uart_init();
console_init();
- pll_reset();
-
- msr_init();
+ cs5535_early_setup();
+ pll_reset();
+ //msr_init();
/* Halt if there was a built in self test failure */
//report_bist_failure(bist);